Reminder!

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Dear Colleague,

VLSI Society of India and IEEE Circuits and Systems Society
(Bangalore Chapter) proudly announce the second International
Workshop on Interconect Design and Variability (IDV 2007) - the
workshop will be held in Bangalore during Dec 13-14. The venue is
Hotel Atria. The details of the program are now available from

http://vlsi-india.org/vsi/download/events/2007/idv-blr-dec07.pdf

Experts in the field of VLSI interconnects and variability will make
presentations on some of the hottest topics. Two panel discussions
are included to provide scope for free discussion. The list of
speakers includes:

Juan C. Rey, Mentor Graphics Corporation
Kazuya Masu, Tokyo Institute of Technology
Ersed Ackasu, OEA International, Inc.
Noel Menezes, Intel Corporation
Sachin Sapatnekar, University of Minnesota
Tom Williams, Synopsys
Vish Sundararaman, Texas Instruments Inc., Dallas
Nishath Verghese, Cadence
Nagaraj, N.S. Texas Instruments Inc., Dallas
Madhav P. Desai, IIT Bombay
Vani Prasad, Freescale Semiconductors
Vidyasagar Ganesan, AMD


The workshop will be useful to professionals as well as faculty and
students who are looking for research topics.

If you have difficulties viewing this announcement, please write to
vsisecy@... for a copy.

Registrations are now open. Please do an on-line registration to
receive a confirmation. You will have to follow this with a payment
by DD/cheque as per the instructions given in the announcement.
Please do the registrations early, since the number of seats is
limited.

Regards


C.P. Ravikumar

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