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VLSI Society of India announes the fourth workshop on Design Verification Methodologies (DVM 2008) at Hotel Capitol, Bangalore during April 25-26.
Nanotechnologies have ushered in System-On-Chip designs with 50 million gates. Functional and timing verification of such designs is a formidable task. Design Verification has been known to be biggest contributor to the design cycle time. Statistics also indicate that design respins are often due to functional bugs detected late.
Cutting down the time for verification is one of the major goals of design teams across the globe. Many new methodologies have emerged towards solving this problem. This two-day workshop is intended as a forum to discuss the new trends and methodologies for Design Verification. It is also a forum to share current practices in Design Verification.
Speakers in the workshop include:
Prabhat Agarwal, Sankalp Semiconductor
Aniruddha Baljekar, NXP Semiconductors
Ansuman Banerjee, Interra Systems India
Gurudutt Bansal, Cadence Design Systems
Vishal Choudhary, NXP Semiconductors
Pallab Dasgupta, IIT Kharagpur
Kaushik De, Synopsys India
Sainath Karlapalem, NXP Semiconductors
Raj Mitra, Texas Instruments India
Abhijit Ray, Cadence Design Systems
Badri Seshadri, NXP Semiconductors
Pradip Thaker, Analog Devices Inc.
Srinivasan Venkataramanan, Synopsys India
Haridas Vilakathra, NXP Semiconductors
Registrations are now open. Please refer to the home page of the workshop at:
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