ISLPED 2008 Technical Program

Monday August 11, 2008

08:30-08:45

Welcome by General and Program Co-Chairs

08:45-09:45

Jaswinder Ahuja Towards a Green Electronic World : A Collaborative Approach

09:45-10:00

Break

10:00-12:00

Variation Tolerant Circuits (1.1.2) Chair: Niraj Bindal Co-Chair: Chris Kim

Power Optimizations (2.1.1) Chair: Wolfgang Nebel Co-Chair: Nagarajan Ranganathan

Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits

Dynamic Virtual Ground Voltage Estimation For Power Gating

Optimal Technology Selection for Minimizing Energy and Variability in Low Voltage Applications

A Mathematical Solution to Power Optimal Pipeline Design by Utilizing Soft Edge Flip-Flops

Post-Silicon Programmed Body-Biasing Platform Suppressing Device Variability in 45 nm CMOS Technology

Power-Gating-Aware High-Level Synthesis

Enhancing Beneficial Jitter Using Phase-Shifted Clock Distribution

A Parallel and Randomized Algorithm for Large-Scale Dual-Vt Assignment and Continuous Gate Sizing Problem

Multiple Power-Gating Domain (multi-VGND)

12:00-13:00

Lunch

13:00-15:00

Power Delivery (1.1.3) Chair: Swarup Bhunia Co-Chair: Radu Zlatanovici

Variation-Aware Optimizatuions (2.1.2) Chair: Bharadwaj Amrutur Co-Cair: Vishwani Agarwal

A Multi-Story Power Delivery Technique for 3D Integrated Circuits

An Expected-Utility Based Approach to Variation Aware VLSI Optimization Under Scarce Information

Energy Harvesting Photodiodes with Integrated 2D Diffractive Storage Capacitance

SRAM Methodology for Yield and Power Efficiency: Per-Element Selectable Supplies and Memory Reconfiguration Schemes

Reducing Wakeup Latency and Energy of MTCMOS Circuits via Keeper Insertion

Row/Column Redundancy to Reduce SRAM Leakage in Presence of Within-Die Delay Variation

Low-Power, High-Accuracy Timing Systems for Efficient Duty Cycling

Reliability-centric Gate Sizing with Simultaneous Optimization of Soft Error Rate, Delay and Power

Variation-Aware Gate Sizing and Clustering for Post-Silicon Optimized Circuits

15:00-15:15

Break

15:15-17:15

Tutorial: Power Management Solutions for Computer Systems and Datacenters Kathick Rajamani

Low Voltage Logic and Memory (1.1.1) Chair: Hiroaki Suzuki (Renesas) Session Co-Chair: Matt Ziegler

Tutorial: Low Power Design under Parameter Variations Kaushik Roy Swarup Bhunia

Error-Resilient Low-Power Viterbi Decoders

Increasing Minimum Operating Voltage (VDDmin) with Number of CMOS Logic Gates

Thermal Analysis of 8-T SRAM for Nano-Scaled Technologies

Analyzing Static and Dynamic Write Margin for Nanometer SRAMs

17:15-18:45

Panel: "Penalty for power reduction – Performance or Schedule or Yield?"

Tuesday August 12, 2008

08:30-10:00

Adaptive Algorithms for Energy-Efficient Applications (2.3) Chair: Chi-Ying Tsui Co-Chair: Karthick Rajamani

Multi-Core Power Optimization (2.2.2) Chair: Mary Jane Irwin Co-Chair: Joerg Henkel

Caching for Bursts :C-Burst: Let Hard Disks Sleep Well and Work Energetically

Proactive Temperature Management in MPSoCs

3-Tier Dynamically Adaptive Power-Aware Motion Estimator for H.264/AVC Video Encoding

Entry Control in Network-on-Chip for Memory Power Reduction

Energy Conservation by Adaptive Feature Loading for Mobile Content-Based Image Retrieval

PowerAntz: Distributed Power Sharing Strategy for Network on Chip

Extending the Lifetime of Media Recorders Constrained by Battery and Flash Memory Size

10:00-10:15

Break

10:15-11:15

Norm Jouppi, HP System Implications of Integrated Photonics

11:15-12:15

Poster Session

Design Contest Session

Total Power Minimization of Asynchronous Circuits

O2C: Occasional Two-Cycle Operations for Dynamic Thermal Management in High Performance In-Order Microprocessors

Low Power High Bandwidth Amplifier with RC Miller and Gain Enhanced Feedforward Compensation

Single stage static level shifter design for subthreshold to I/O voltage conversion

Power Reduction in On-Chip Interconnection Network by Serialization

A Probabilistic Approach for Full-chip Leakage Estimation

Bus Encoding for Simultaneous Delay and Energy Optimization

Frequency Planning for Multi-Core Processors Under Thermal Constraints

Reducing Leakage Power in Dual-Vt Circuits by Exploiting Temperature Effect on Nano-CMOS Standard Cells

Variability of Flipflop Timing at Subthreshold Voltages

Low power Current Mode Receiver with Inductive Input Impedance

Analytical results for design space exploration of multi-core processors employing thread migration

A Physical Level Study and Optimization of CAM-Based Checkpointed Register Alias Table

12:15-13:15

Lunch

13:15-14:15

Tutorials

Memory Systems & Special-purpose Hardware (1.2.1) Chair: Vasantha Erraguntla

Low-Power Challenges in Analog and Mixed-Signal Front-ends (1.3.1) Chair: Kameran Azadet (LSI)

Tutorial: A Tutorial on Test Power Vishwani Agrawal

Enhancing Energy Efficiency of Processor-Based Embedded Systems through Post-Fabrication ISA Extension

Optimal power and noise allocation for analog and digital sections of a low power radio receiver

Energy-Efficient MESI Cache Coherence with Pro-Active Snoop Filtering for Multicore Microprocessors

Design of low power short-distance optoelectronic transceiver front-ends with scalable supply voltages and frequencies

14:15-15:15

Tutorial: Delivery for High Performance Microprocessors Srikanth Balasubramanian

A Low Power Layered Decoding Architecture for LDPC Decoder Implementation for IEEE 802.11n LDPC Codes

On the Power Efficiency of Cascode Compensation over Miller Compensation in Two-Stage Operational Amplifiers

A Secure and Low-Energy Logic Style Using Charge Recovery Approach

A 1-V Piecewise Curvature-corrected CMOS Bandgap Reference

Word-Interleaved Cache: An Energy Efficient Data Cache Architecture

A 1.8/2.4-GHz Dualband CMOS Low Noise Amplifier Using Miller Capacitance Tuning

15:15-15:30

Break

15:30-16:30

Tahir Ghani, Intel Innovations to Extend CMOS Nano-transistors to the Limit

16:30-18:00

Panel: "Getting the next 100X power improvements in a multicore world: where should we focus on?"

19:00

Banquet/Cultural Event

Wednesday August 13, 2008

08:00-09:30

Industry Session

Runtime Power and Thermal Management (2.2.3) Chair: Rabi N. Mahapatra Co-Chair: Massimo Poncino

Srikanth Jadcherla SOC Designs in the Energy Conscious Era

Simultaneous Optimization of Battery-Aware Voltage Regulator Scheduling with Dynamic

Expected System Energy Consumption Minimization in Leakage-Aware DVS Systems

Tutorial: Clock Gating for Power Optimization in ASIC Design Cycle : Theory & Practice Sukumar Jairam Madhusudan Rao

Hybrid Dynamic Thermal Management Based on Statistical Characteristics of Multimedia Applications

09:30-09:45

Break

09:45-10:45

Janick Bergeron, Synopsys Advances in Low Power Verification

10:45-12:15

Tutorial: Low power chips: A fabless ASIC perspective Vamsi Boppana

System-Level Power Estimation (2.2.1) Chair: Todd Austin Co-Chair: Naehyuck Chang

A Framework for Energy Consumption Based Design Space Exploration for Wireless Sensor Nodes

Full-System Chip Multiprocessor Power Evaluations Using FPGA-Based Emulation

Noninvasive Leakage Power Tomography of Integrated Circuits by Compressive Sensing

12:15-13:15

Lunch

13:15-15:15

Tutorial: On Leakage Currents: Sources and Reduction for Transistors, Gates, Memories and Digital Systems Wolfgang Nebel

Microarchitectural techniques (1.2.2) Chair: Masaaki Kondo Co-Chair: Koji Inoue

Impact of DVFS on the architectural vulnerability of GALS architctures

Instruction-driven clock scheduling with glitch mitigation

Thread Fusion

Power-Efficient Clustering via Incomplete Bypassing

Lazy Instruction Scheduling: Keeping Performance, Reducing Power

15:15-15:30

Break

15:30-16:30

Todd Austin, U of Michigan On the Rules of Low-Power Design (and How to Break Them)

16:30-17:30

Takayasu Sakurai, Univeristy of Tokyo Next-generation Low-power Design and System

17:30

Closing Remarks