1.hw do u say a processor as an 8 bit / 16 bit one , by means of addr lines r data lines 2.wht do u mean by APEX20KE devices and wht do u mean by speed-grade...

1.still iam not clear with false path.so explain me in detail.explanation was previously gn by one of the member based on mux, thr they mentioned false path as...

1. what do u mean by vo simulation 2. what do u mean by false path --let me give my answer can u say whether it is correct r not ans: consider as wiring...

Hello, To answer ur second question: Ur understanding of FALSE-PATH is wrong. This is more related to timing closure and not to simulation...or way u connect ...

Abhay mentioned it rightly that "False Paths" come into picture when we want to attain Timing closures. That means we want a module or a design to be run at...

thank u for explaining false path kalaivani ... Do you Yahoo!? Everyone is raving about the all-new Yahoo! Mail Beta....

thanks both of u for explaining false path kalaivani sandip gaikwad <sandy283792000@...> wrote: Abhay mentioned it rightly that "False Paths" come into...

thanks for both of u for explaining false path kalaivani premrajan_18@... sandip gaikwad <sandy283792000@...> wrote: Abhay mentioned it rightly...

Hai all, can anyone can guide me to develop a simple driver code in c to check my simple fifo design written in verilog.(ie)iam in need to develop to check...

Question to ask...is the system time available. Verilog *generally* runs on some target hardware, such as a FPGA or CPLD. Inherant to those devices, is the...

s the sys time is available.iam an intermediate in verilog field.i need to find sys time using verilog program.i ususally run the program using modelsim ( iam...

frnd i got the sys time using perl script .ok thanks regards kalaivani micro_eng2 <micro_eng2@...> wrote: Question to ask...is the system time available....