I have not done any verilog coding in several years I hired a consultant to
get me back up to speed. He looked at my code and said this was bad:

Always @(posedge clk) begin

If (reset) begin

Cmd_ack<= 0;

End else begin

Cmd_ack<=0; //set default condition

Case (state)

SOME_STATE: begin

Cmd_ack<=1; //set high for one clock.

End

// other states

Endcase

End

End

I see code on opencores.org and such that sets a default condition like
above rather than making sure the cmd_ack is set in every case statement.
Does anyone know if the default like this OK for synthesizeable code?

Thanks
Trampas