Hello all, I am relatively a new user of modelsim simulator as far as VHDL is concerned.I have some few questions for which I would like clarification and...
amar desai
amar2077@...
Jul 15, 2003 1:53 pm
165
Hello All, can anyone tell me what are the majorand minor parameters that usually go in when we decide the clock frequency of a perticular Design... example...
amar desai
amar2077@...
Jul 22, 2003 2:40 pm
166
Hi all, I am working on "Implementation of Serpent algorithm on an FPGA" in Handel-C for my dissertation in M.S and for that i need the verilog code for ...
Hi Folks, I am working on conversion of a legacy schematic into verilog. Require help in the usage of the Viewdraw tool for viewing of the Schematics. Have...
hiii.. iam kiran,new to this group...i need help in writing the verilog code for the attached ckt,.. thanx in advance... ... Do you Yahoo!? Yahoo! SiteBuilder...
Note: forwarded message attached. hi i hope the code posted would be usful for designing in verilog "i hope some one posts fir filter sample code plz people...
hi all, this is doc i found while searching for verilog code for designing fir filter. i hope it is quite usful to u !! plz people share ur filter verilog code...
Hi All, I have done PG Diploma in VLSI Design from C-DAC and looking for an break is it possible to do some thing? Ramesh kommineni <kommineni911@...>...
Hello there, I'm new to this group as well as to Verilog programming.I have a question regarding the "WIRE" and "REG" variable of it, ie is there any intuitive...
Faisal, wires are like interconnects (in between logic gates...everything is a wire, if not something else)..and any variable which is having a value assigned...
Hello friends, my name is kannan and I am working as vlsi design engg. at chennai. Now I want verilog coding for usart or uart model, can anyone have that....
... question regarding the "WIRE" and "REG" variable of it, ie is there any intuitive way to remember where to use "wire" and where to use "reg"?coz i get...
hi can u help me in finding some good examples for writing research proposal related signal processing architecture in VLSI. also if u can tell me some current...
Hello I am a recruiter for the EDA industry. I am working for a start up out of Cambridge England. I am looking for a Verilog expert that knows C++ well that's...
Hi all i have to wriote LCD Display driver code(verilog) to see my counter output on LCD display in FPGA Kit ...i urgently need guidance to know how can i do...
Hi dheeraj.. u need to know the what LCD display you are using first first of all if its an active low or active high output.. Then u need to only use the case...
Hello friends, I am vlsi design engg. from India. Can anybody have coding that is possible for synthesis purpose(i.e board level program) for shift register...
hi.. check on opencores.org for more info wrt codes.. Vivek kannan <kannvino@...> wrote: Hello friends, I am vlsi design engg. from India. Can anybody...
Brandon Haave IC Design and Automation Search 970-532-7088 brandon@... Unfortunately we filled the AE position I placed on this site early this week....
Hi All Fst of all thanx Vivek i have designed the LCD display driver andf your hint was sufficient for directing me towards solutrion.....I have another...
Hi dheeraj, U need to be more clear wrt the controller. DO u have to design the controller using statemachine or is it just a combinational circuit?? Lemme...
Sir/Ma'am, I have done my masters from university of essex and have done my dissertation using Handel-C. I would like to know whether there is any oppurtunity...
hi, I want to make a simulation regarding Flip-flops but I dont know how to handle it..plz mail me(if possible) a sample of flip flop working or plz explain...
Here You go... // Negative Edge-Triggered D Flip Flop with Asynchronous clear // clear is active high // D_FF clears whenever clear goes high. It does not wait...
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