hi can u help me in finding some good examples for writing research proposal related signal processing architecture in VLSI. also if u can tell me some current...
Hello I am a recruiter for the EDA industry. I am working for a start up out of Cambridge England. I am looking for a Verilog expert that knows C++ well that's...
Hi all i have to wriote LCD Display driver code(verilog) to see my counter output on LCD display in FPGA Kit ...i urgently need guidance to know how can i do...
Hi dheeraj.. u need to know the what LCD display you are using first first of all if its an active low or active high output.. Then u need to only use the case...
Hello friends, I am vlsi design engg. from India. Can anybody have coding that is possible for synthesis purpose(i.e board level program) for shift register...
hi.. check on opencores.org for more info wrt codes.. Vivek kannan <kannvino@...> wrote: Hello friends, I am vlsi design engg. from India. Can anybody...
Brandon Haave IC Design and Automation Search 970-532-7088 brandon@... Unfortunately we filled the AE position I placed on this site early this week....
Hi All Fst of all thanx Vivek i have designed the LCD display driver andf your hint was sufficient for directing me towards solutrion.....I have another...
Hi dheeraj, U need to be more clear wrt the controller. DO u have to design the controller using statemachine or is it just a combinational circuit?? Lemme...
Sir/Ma'am, I have done my masters from university of essex and have done my dissertation using Handel-C. I would like to know whether there is any oppurtunity...
hi, I want to make a simulation regarding Flip-flops but I dont know how to handle it..plz mail me(if possible) a sample of flip flop working or plz explain...
Here You go... // Negative Edge-Triggered D Flip Flop with Asynchronous clear // clear is active high // D_FF clears whenever clear goes high. It does not wait...
hello folks i am a new member of this group. I am really desperate to find out whether my models in Verilog AMS can be simulated using spectreRF. kindly...
Hi all Please help me in this !!!!! I am in my first semester a.I have to design a controller chip for the CD_DVD controller .I have already dont the coding...
hi, everyone. is there anybody who has verilog files or information of verilog codes for interpolation fir filter? please help me. i need files. thanks and...
i may useful for you ... From: taekim94 <taekim94@...> To: <verilog@yahoogroups.com> Sent: Thursday, November 27, 2003 5:08 PM Subject: [verilog]...
ramaraju.elec
ramaraju.elec@...
Nov 28, 2003 5:04 am
198
... [Sorry for the slow response] SpectreRF can handle Verilog-AMS, however support may vary. I did some models of latches for someone to use in a PLL design a...
hey Mr.Kev Thanks for your reply. We have managed to get hold of the cadence ams 2.0 version for our models. We are running ncsim from the cadence ams suite....
Hi I'm a new member of group. Would you please let me know if there is any tutorial doc about Verilog-A and Verilog-AMS. I've just strated studing it. Regards ...
... Verilog-A and Verilog-AMS. I've just strated studing it. ... Dan Fitzpatrick wrote a book - Analog Behavioral Modeling With the Verilog-A Language ...
Hello there, I'm working to design a processor in verilog. I have written all the lower level modules like ALU, PC and mux control etc. But when i instantiate...
hi, U may need to 1) declare appropriate width for the signals (wires) in top module. 2)Make proper signal connection (connect clock to clock_DUT inputs, reset...
Hi, I hope you have written all the modules including top level in single file but please avoid this style. You try to have separate files for the modules...
siva kumar
prsiva2000@...
Dec 2, 2003 9:09 am
207
Thanks Ashwath n Siva, The prob is with my lower level module ie with prog counter logic as i was not initializing with 0,thinking that my micro program memory...
Hi guys... I am probably mailing for the first time in this group. I need help I am seriously looking for VLSI design jobs here in india and i am finding it ...
Hello, I am trying to find a free verilog compiler/simulator than can basically compile and perform synthesis and then simulate. I am a beginner at verilog so...
Hello people !!! I am a new member of this group . I am looking for a free verilog synthesis tool for one of my graduate projects.If anyone has any idea do let...
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