hello folks i am a new member of this group. I am really desperate to find out whether my models in Verilog AMS can be simulated using spectreRF. kindly...
Hi all Please help me in this !!!!! I am in my first semester a.I have to design a controller chip for the CD_DVD controller .I have already dont the coding...
hi, everyone. is there anybody who has verilog files or information of verilog codes for interpolation fir filter? please help me. i need files. thanks and...
i may useful for you ... From: taekim94 <taekim94@...> To: <verilog@yahoogroups.com> Sent: Thursday, November 27, 2003 5:08 PM Subject: [verilog]...
ramaraju.elec
ramaraju.elec@...
Nov 28, 2003 5:04 am
198
... [Sorry for the slow response] SpectreRF can handle Verilog-AMS, however support may vary. I did some models of latches for someone to use in a PLL design a...
hey Mr.Kev Thanks for your reply. We have managed to get hold of the cadence ams 2.0 version for our models. We are running ncsim from the cadence ams suite....
Hi I'm a new member of group. Would you please let me know if there is any tutorial doc about Verilog-A and Verilog-AMS. I've just strated studing it. Regards ...
... Verilog-A and Verilog-AMS. I've just strated studing it. ... Dan Fitzpatrick wrote a book - Analog Behavioral Modeling With the Verilog-A Language ...
Hello there, I'm working to design a processor in verilog. I have written all the lower level modules like ALU, PC and mux control etc. But when i instantiate...
hi, U may need to 1) declare appropriate width for the signals (wires) in top module. 2)Make proper signal connection (connect clock to clock_DUT inputs, reset...
Hi, I hope you have written all the modules including top level in single file but please avoid this style. You try to have separate files for the modules...
siva kumar
prsiva2000@...
Dec 2, 2003 9:09 am
207
Thanks Ashwath n Siva, The prob is with my lower level module ie with prog counter logic as i was not initializing with 0,thinking that my micro program memory...
Hi guys... I am probably mailing for the first time in this group. I need help I am seriously looking for VLSI design jobs here in india and i am finding it ...
Hello, I am trying to find a free verilog compiler/simulator than can basically compile and perform synthesis and then simulate. I am a beginner at verilog so...
Hello people !!! I am a new member of this group . I am looking for a free verilog synthesis tool for one of my graduate projects.If anyone has any idea do let...
http://www.verilog.net/free.html https://www.altera.com/support/software/download/altera_design/mp2_st udent/dnl-student.jsp these are the tools we use for...
ASSALAM O ALAIKUM TO ALL Is there any replacement for leonardo spectrum. plz mail me some useful softwares in this regard USMAN HAI ... Do you Yahoo!? ...
hello there, Can any body suggest me which sorting algorithm should i use for sorting a 128 elements array (8 bit n 2's complement) from HDL( verilog) point of...
Hi friends My name is Krishna Kishore Balam and I am doing MS in electrical engineering. Hi kannan I also have one code for UART which works very fine. If you...
hi, I think "systolic array" should help u in this regard. Ashwath ... __________________________________ Do you Yahoo!? New Yahoo! Photos - easier uploading...
hii guys!!! iam final yr engg student. i am doing my proj in vlsi.i want to know where i can get a synthesiser tool for code in verilog . i any body knows...
Hi Ashwath, Thanks for the 'algo' tip. It would be great if you could send me some more info about this 'Systolic Insertion algo'.As i could not find any...
hi faisal, It has been long time i worked on algos, at the moment i dont have any material also. I think in web there are good "Implementaion Notes". Not only ...
hi guys, I am aware that synthesis tools are intelligent enough to optimize a state machine.Can any of the Synthesis tools detect the Deadlock states in the ...
I want join ur yahoo group because I doing study on how to write verilog code for state machnine. Regard CPK1023 ... __________________________________ Do you...
hi.. iam a new member in this group...iam designing a DSP processor in my research work...i need help in writing the verilog code for RAM... 4k *16 bit RAM...
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