Hi:
     I now is learning JTAG,but I can't find learning documents about
JTAG,
Can you recommend something for me?
Thank you
Yang

Hi,

DC means Design Compiler, a synthesis tool from Synopsys. PrimeTime is a
static timing analysis tool from Synopsys also.

regards, Albert

----- Original Message -----
From: "draggon" <draggon@...>
To: <verilog@egroups.com>
Sent: Wednesday, September 06, 2000 10:34 AM
Subject: [verilog] About Several EDA terms


>
> Hi:
>    everyone,I like this group.I meet several EDA terms I don't
> understand:
>    PhysOpt, DC, PrimeTime, FlexRoute, reoptimize_design, WLMs, BOA, and
> BRT
>    Who can interpretate for me!
>
> Regards
> Yang
>
>
>
>

Hi:
    everyone,I like this group.I meet several EDA terms I don't
understand:
    PhysOpt, DC, PrimeTime, FlexRoute, reoptimize_design, WLMs, BOA, and
BRT
    Who can interpretate for me!

Regards
Yang

draggon@... said:
>  I use Verilog-XL for verilog simulation!I find that run "always"
> first instead of "intial".I am comfused!

It is a common programming error in Verilog to have an initial statement
initializing a clock at time zero, like so:

     initial clk = 0;
     always @(negedge clk) begin ... end

This is a time-0 race. I get a lot of bug reports to my compiler from
people saying that this "works with XL but not with Icarus Verilog" So
I'm sensitive to this common situation:-)

See FAQ: <http://www.icarus.com/eda/verilog/FAQ.html>.

I think someone finally determined that initial and always blocks are
executed from top down in Verilog-XL. That is, the threads that appear
first in the text are started first. So check if reordering the statements
causes different behavior for you.

It is possible, though, that in order to make the simulator more resilient
to time-0 races like I described, the XL compiler may start always statements
first.  (I've considered doing that myself.) If this is so, it doesn't make
your program any less buggy, it just makes the simulation appear to function
correctly.

--
Steve Williams                "The woods are lovely, dark and deep.
steve@...              But I have promises to keep,
steve@...            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Hi:
     I use Verilog-XL for verilog simulation!I find that run "always"
first instead
of "intial".I am comfused!
    for example
     intial
        begin
           clk<=0;
        end
     always @(posedge clk)
          begin
             .......
              end

    when simulation, Verilog-XL first run "always @(posedge clk" ,and not
the "initial"

why??


Regards
Yang

Hi, you may pay a visit to http://www.iazone.net . It's new open but in
traditional Chinese only at this moment.

regards, Albert

----- Original Message -----
From: "draggon" <draggon@...>
To: <verilog@egroups.com>
Sent: Tuesday, August 29, 2000 3:30 PM
Subject: [verilog] Please recommend something about verilog synthesis!


> Hi:
>     I am now studing verilog and logic synthesis!
>     I need something about verilog synthesis,such as free software,
> books, paper, www web and other documents.
>    Please recommend something for me!
>
>
> regards
> Yang
>
>
>
>
>

Hi:
     I am now studing verilog and logic synthesis!
     I need something about verilog synthesis,such as free software,
books, paper, www web and other documents.
    Please recommend something for me!


regards
Yang

Oops.  Was in a hurry.  But now I know the there *are* lurkers out there.

> -----Original Message-----
> From: John Cooley [mailto:jcooley@...]
> Sent: Monday, August 28, 2000 12:59 PM
> To: verilog@egroups.com; snake_luo; Elliot Mednick
> Subject: RE: [verilog] how does synthesis tool implement full_
>
>
> I think you mean http://www.DeepChip.com Elliot; there is no "deepblue".
>
>     - John
>
>
>
>
> >From
> sentto-1087861-7-967464970-jcooley=world.std.com@...
> om  Mon Aug 28 08:17:37 2000
> >Return-Path:
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> Aug 2000 08:15:50 -0400 (EDT)
> >To: "snake_luo" <snake_luo@...>, <verilog@egroups.com>
> >Message-ID: <000e01c010ec$db9b7ae0$0e08a8c0@...>
> >X-Priority: 3 (Normal)
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> >From: "Elliot Mednick" <elliot@...>
> >MIME-Version: 1.0
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> >Date: Mon, 28 Aug 2000 08:38:24 -0400
> >Subject: RE: [verilog] how does synthesis tool implement full_
> >Content-Type: text/plain; charset=US-ASCII
> >Content-Transfer-Encoding: 7bit
> >Status: O
> >X-Status:
> >
> >See Cliff Cummings' treatise on the topic in http://www.deepblue.com or
> >http://192.215.73.62/items/0332-01.html.
> >
> >--Elliot
> >
> >> -----Original Message-----
> >> From: snake_luo [mailto:snake_luo@...]
> >> Sent: Monday, August 28, 2000 11:30 AM
> >> To: verilog@egroups.com
> >> Subject: [verilog] how does synthesis tool implement full_
> >>
> >>
> >> Recently,I learned from a book that:in order to avoid unexpected
> >> latch,one way is using "full_case statement.I wonder,how does
> >> synthesis tool do with this statement?
> >> Thanks!
> >
> >--
> >Elliot Mednick                              51 Sawyer Rd, Suite 110
> >Processor Architect                         Waltham, MA. 02453
> >Lexra, Inc.                                 (781) 899-5799 x805
> >elliot@...                            (781) 899-5769 fax
> >
> >
> >
> >
> >
>

I think you mean http://www.DeepChip.com Elliot; there is no "deepblue".

     - John




>From sentto-1087861-7-967464970-jcooley=world.std.com@returns.onelist.com  Mon
Aug 28 08:17:37 2000
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>From: "Elliot Mednick" <elliot@...>
>MIME-Version: 1.0
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>Date: Mon, 28 Aug 2000 08:38:24 -0400
>Subject: RE: [verilog] how does synthesis tool implement full_
>Content-Type: text/plain; charset=US-ASCII
>Content-Transfer-Encoding: 7bit
>Status: O
>X-Status:
>
>See Cliff Cummings' treatise on the topic in http://www.deepblue.com or
>http://192.215.73.62/items/0332-01.html.
>
>--Elliot
>
>> -----Original Message-----
>> From: snake_luo [mailto:snake_luo@...]
>> Sent: Monday, August 28, 2000 11:30 AM
>> To: verilog@egroups.com
>> Subject: [verilog] how does synthesis tool implement full_
>>
>>
>> Recently,I learned from a book that:in order to avoid unexpected
>> latch,one way is using "full_case statement.I wonder,how does
>> synthesis tool do with this statement?
>> Thanks!
>
>--
>Elliot Mednick                              51 Sawyer Rd, Suite 110
>Processor Architect                         Waltham, MA. 02453
>Lexra, Inc.                                 (781) 899-5799 x805
>elliot@...                            (781) 899-5769 fax
>
>
>
>
>

See Cliff Cummings' treatise on the topic in http://www.deepblue.com or
http://192.215.73.62/items/0332-01.html.

--Elliot

> -----Original Message-----
> From: snake_luo [mailto:snake_luo@...]
> Sent: Monday, August 28, 2000 11:30 AM
> To: verilog@egroups.com
> Subject: [verilog] how does synthesis tool implement full_
>
>
> Recently,I learned from a book that:in order to avoid unexpected
> latch,one way is using "full_case statement.I wonder,how does
> synthesis tool do with this statement?
> Thanks!

--
Elliot Mednick                              51 Sawyer Rd, Suite 110
Processor Architect                         Waltham, MA. 02453
Lexra, Inc.                                 (781) 899-5799 x805
elliot@...                            (781) 899-5769 fax

Recently,I learned from a book that:in order to avoid unexpected latch,one way
is using "full_case statement.I wonder,how does synthesis tool do with this
statement?
Thanks!
______________________________________

===================================================================
ÐÂÀËÃâ·Ñµç×ÓÓÊÏä http://mail.sina.com.cn
¾´Çë¹Ø×¢ 8ÔÂ27ÈÕ19µã45·Ö ºþÄÏÎÀÊÓ<õ¹åÖ®Ô¼> ÐÂÀË°ÂÔËÇéÂÂÌØʹ¾öÈü
http://ad2.sina.com.cn/ads/olympics/

Suzanne Southworth
CynApps
"http://www.cynapps.com"

______________________________________

===================================================================
ÐÂÀËÃâ·Ñµç×ÓÓÊÏä http://mail.sina.com.cn
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http://ad2.sina.com.cn/ads/olympics/

Hi:
     It is said that it's better to use RTL description instead of gate
level description in "Gloldern Refence" of Doulso corporation.
the followings is original text in "Gloldern Refence" :
    Partition the design into small functional blocks, and use a
behavioural style
for each block. Avoid gate level descriptions except for critical parts
of the
design.
     why?


Regards

Hi:
     I am studing verilog now£¡
   what is "transparent latch"
     synthesize the following verilog code:
     always @(input)
         if(ena)
            case(r1)
                0: r2<=1;
                1:r2<=0;
           endcase
     It is said that code will be systhesized to a "transparent latch",I can't
understand if!

I am looking for a relatively cheap, or even free Verilog to VHDL
translator.  If anyone has anything please get back to me.

Sincerely,
Charles

Hi all,

Hope you had a good time at DAC if you were there. It was interesting
to see that more companies were talking about Verilog-A and at least
a few are promising Verilog-AMS. Unfortunately the OVI standard was
rather slow in arriving and missed inclusion into the IEEE Verilog
2000 standard, but that does mean there will be lots of time to fix
it at the IEEE - so now is the time to get involved if you are
interested (post back if you want details of outstanding issues).

The lastest update of v2k (00.20) is now available from the
'download' area at 'http://www.v-ms.com'. Once again, it is mostly
a bug-fix release, but I have uploaded executables as well this
time (Sparc & x86). Currently I'm using RedHat 6.2 Linux and Solaris
2.7 (there is a bug in pre 6.2 RedHat).

Regards,
Kev.

For people in the San Francisco area and interested in open source EDA:

I am happy to announce that the first, of what I hope will become a
monthly, open source EDA dinner will be held on Wednesday, February 9,
at 7:15 pm.  The location is the Hangen Szechuan Restaurant at 134
Castro St., in downtown Mountain View. (tel: 650-964-8881)

This restaurant is across the street from the Castro Cal Train station
and the new light rail terminus.  For those arriving by car, there is a
large (free) parking structure behind the restaurant.  Drive around the
block to the entrance.

There is no agenda.  This is an opportunity for people, who may know
each other only by email, to meet and talk casually, and for others to
learn about what is happening in the open source EDA movement.  I
anticipate much lively conversation.

I would appreciate an RSVP from those planning to attend so I can update
the restaurant with a more accurate head count.

See you there,
Rick Munden
munden@...
650-694-5523

In a message dated 1/29/00 8:16:04 AM Eastern Standard Time,
verilog@egroups.com writes:

> eGroups Daily Digest: verilog has 1 new messages.
>  Click here http://www.eGroups.com/list/verilog/?start=11 to read them.
>
>  -----------------------------------------------------------------
>  011. ravi                      Re: V2000 00.18 Release (mostly bug fix)
>  ---------------------------------------------------------------

Thanks for the info!

Suzanne Southworth
Cyn Apps
http://www.cynapps.com

v2k-00.18

The Verilog-dump option now supports `line directives, and command line +define/+undef options allow using v2k as a preprocessor - get back to me if you want any special pre-processor functions added (or bugs fixed).

If any of you Silicon Valley residents want to discuss this project over (say) beer I'll be there next week.

Regards,
Kev.

v2k-00.17

It is now distributed under the GNU Lesser General Public License, and as I consider it stable enough for more general distribution I've removed the password protection. There is also a binary distribution for Linux and Solaris - once unpacked and installed you should be able to run it ( v2k <verilog files> -elab -shell ) and browse through a design hirearchy. NB: I consider the code as alpha quality.

This release corresponds (more or less) to the end of "Phase 1" in the project plan: "Build the Verilog-AMS parser, intermediate form writer, and then the elaborator"

Currently the only candidate for a "Phase 2" plug-in is Spice-3f4, if you have any better ideas I'll be glad to hear about them. E.g. do you have any internal company simulators that need a Verilog front-end?

After that, I might rearrange the remaining tasks and build an Open System C compatible code generator and simulation kernel for the Verilog behavioral code.

Regards,
Kev.

eda-@... wrote:
original article:http://www.egroups.com/group/verilog/?start=6
> > I was wondering if anyone has tried it out?  What do you think of
the
> > concept?
>
> I downloaded it...
> 5) The "really neat" Verilog->Cynlib file twister is not present in
the
>      OSS version.  I have to look at the license and see if there's
anything
>      that precludes OSS developers from distributing their own.  I
have
>      a bare antlr LL(2) grammar laying around for 1364 and this could
be a
>      fun project.  Interestingly, cynlib classes could be used as an
>      intermediate format for verilog compilation.  Not the full
language,
>      but a decent synthesizable subset.

I have most of a Verilog parser/elborator (the v2000 project) which I
can
use as a front-end to cynlib, i.e. generate cynlib style C++. My
understanding
is that the cynlib syntax has been offered (to OVI) as an open standard,
and they cannot object to people doing this kind of thing.

> As far as the concept goes, it's a decent idea.  What they've done is
added
> pseudoparallel execution to C++ through some class library tricks.  By
> doing that, HDL simulation is made possible.  I give them an A for
effort
> on this one.  (Though I'm wondering if something like cilk can be
adapted
> to do the same thing..and better b/c it's designed for SMP.)

It's sort of like VCS - but without bothering with the Verilog :-)

> Most of the problems that I can see would be related to hardware
designers
> themselves and not cynlib itself.  Convincing teams to try out cynlib
when
> they know verilog/vhdl already "works" may be a tough pill to swallow.
> Additionally, the relative newness of the product may scare off a lot
of
> people because they'd have questions like, "does it really synthesize
into
> what the cynlib source specs out?"

Might be a good vehicle for IP though.

> It looks like it has a lot of potential..if anything, I can see it
being
> used as a quick and dirty back-end for HDL simulation, even if it
never
> does get used for its intended use of being an "all in one" solution.

Might use it as a "quick & dirty back-end" myself.
I think an 'all-in-one' solution is going to require more effort, and
more open-source freeware.

> Their distro does need a little bit more work.  Non-toy examples would
> go a long way to convincing designers that the product has potential.

'jra' tends to be a bit Sparc/Sun centric in his thinking.
Maybe if/when I write the Verilog->Cynlib translator, we can just
translate some Verilog examples :-)

> For "freedom of speech" type fans, the actual sourcecode is quite
small and
> I don't think it would be too too difficult for someone to eventually
make
> a GNU knockoff based on the same concept/API.  I have to look at the
OSS
> license for it and see what the development restrictions are.  Time to
> forward it off to Bruce Perens...

That's what I was thinking [ after I do the front end :-) ]

Kev.

> I was wondering if anyone has tried it out?  What do you think of the
> concept?

I downloaded it yesterday and checked it out..some observations:

1) There's a 9MB solaris executable sitting in there eating up most of
      the archive.  They really should trim it out..the tgz is 400k then.
2) Few problems with compiling under linux...mainly, I had to change all
      of the gcc instances to g++ (otherwise I got "cc1plus missing" errors)
      and manually copy some files over to where they belong.  No big deal.
      It's plain vanilla c++ so it'll probably compile on anything.
3) For the most part, the examples are "weak" and some appear to do nothing.
      I don't know about you, but I'm really sick of seeing traffic lights...
      The line drawing ones in the instruction manual are nice though.
4) One example created a file named "barf" that had incorrectly written VCD.
      (Zeros throughout the simulation).
5) The "really neat" Verilog->Cynlib file twister is not present in the
      OSS version.  I have to look at the license and see if there's anything
      that precludes OSS developers from distributing their own.  I have
      a bare antlr LL(2) grammar laying around for 1364 and this could be a
      fun project.  Interestingly, cynlib classes could be used as an
      intermediate format for verilog compilation.  Not the full language,
      but a decent synthesizable subset.

As far as the concept goes, it's a decent idea.  What they've done is added
pseudoparallel execution to C++ through some class library tricks.  By
doing that, HDL simulation is made possible.  I give them an A for effort
on this one.  (Though I'm wondering if something like cilk can be adapted
to do the same thing..and better b/c it's designed for SMP.)

Most of the problems that I can see would be related to hardware designers
themselves and not cynlib itself.  Convincing teams to try out cynlib when
they know verilog/vhdl already "works" may be a tough pill to swallow.
Additionally, the relative newness of the product may scare off a lot of
people because they'd have questions like, "does it really synthesize into
what the cynlib source specs out?"

It looks like it has a lot of potential..if anything, I can see it being
used as a quick and dirty back-end for HDL simulation, even if it never
does get used for its intended use of being an "all in one" solution.

Their distro does need a little bit more work.  Non-toy examples would
go a long way to convincing designers that the product has potential.

For "freedom of speech" type fans, the actual sourcecode is quite small and
I don't think it would be too too difficult for someone to eventually make
a GNU knockoff based on the same concept/API.  I have to look at the OSS
license for it and see what the development restrictions are.  Time to
forward it off to Bruce Perens...

Tony

I use ModelSim for both Verilog and VHDL.  For analog Acuson uses
hspice and spiceplus (Cadence Analog Workbench).  I am looking forward
to using a standard analog simulation language like (VHDL/Verilog)-AMS
when one becomes available.

Rick


munde-@... wrote:
original article:http://www.egroups.com/group/verilog/?start=3
> Which of these simulators do you use?
> ----
>
> Please select one or more of the following:
>
>    o VCS
>    o Verilog-XL
>    o NC Verilog
>    o HSpice
>    o UCB Spice 3
>    o Spectre
>    o Saber
>    o Verilog-A (any)
>
>
> by going to the following Web form:
>
>    http://www.egroups.com/vote?id=933848929251
>
> Thank you!
>

CynApps have decided to go the open-source route:

"This is the first significant open source project attempted in EDA, and it has the potential to change both the way hardware is designed and the EDA industry itself. With any luck, things may never be the same again."

[Obviously they havn't noticed the gEDA,ng-spice or v2k projects :-) ]

I was wondering if anyone has tried it out?
What do you think of the concept?

The reason that I ask is that it is based on using C++ class templates for models, which makes it relatively easy to integrate into the v2k Verilog-AMS project (which is also in C++).

Looking forward to your feedback,
Kev.

Which of these simulators do you use?
----

Please select one or more of the following:

    o VCS
    o Verilog-XL
    o NC Verilog
    o HSpice
    o UCB Spice 3
    o Spectre
    o Saber
    o Verilog-A (any)


by going to the following Web form:

    http://www.egroups.com/vote?id=933848929251

Thank you!

Which platform(s) do you prefer to have EDA freeware
working on?

----

Please select one or more of the following:

    o Linux x86
    o Windows 9?
    o Windows NT
    o Linux non-x86
    o Solaris SPARC
    o Solaris X86
    o AIX
    o HP-UX


by going to the following Web form:

    http://www.egroups.com/vote?id=933260898775

Thank you!

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