verilog : Messages : 203-233 of 735

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203	Hello there, I'm working to design a processor in verilog. I have written all the lower level modules like ALU, PC and mux control etc. But when i instantiate...	Faisal Mahmood faysal_m	Dec 1, 2003 10:31 am
204	hi, U may need to 1) declare appropriate width for the signals (wires) in top module. 2)Make proper signal connection (connect clock to clock_DUT inputs, reset...	Ashwath blashwath	Dec 1, 2003 1:59 pm
206	Hi, I hope you have written all the modules including top level in single file but please avoid this style. You try to have separate files for the modules...	siva kumar prsiva2000@...	Dec 2, 2003 9:09 am
207	Thanks Ashwath n Siva, The prob is with my lower level module ie with prog counter logic as i was not initializing with 0,thinking that my micro program memory...	Faisal Mahmood faysal_m	Dec 2, 2003 9:54 am
208	Hi guys... I am probably mailing for the first time in this group. I need help I am seriously looking for VLSI design jobs here in india and i am finding it ...	Rekha Venkataraman rekha_venkat...	Dec 7, 2003 3:54 am
209	Hello, I am trying to find a free verilog compiler/simulator than can basically compile and perform synthesis and then simulate. I am a beginner at verilog so...	cttsao2002	Dec 9, 2003 5:35 pm
210	Hello people !!! I am a new member of this group . I am looking for a free verilog synthesis tool for one of my graduate projects.If anyone has any idea do let...	Chintamani Lonkar mani_bond007	Dec 9, 2003 9:01 pm
211	http://www.verilog.net/free.html https://www.altera.com/support/software/download/altera_design/mp2_st udent/dnl-student.jsp these are the tools we use for...	Nevil Gajera nevilin2001	Dec 9, 2003 9:07 pm
212	http://www.einfochips.com/careers.html -Nevil ... _____________________________________________________________________ ... ...	Nevil Gajera nevilin2001	Dec 9, 2003 9:08 pm
213	hi, u can get a free version of "Icaraus verilog" at the site 'www.opencollector.org'. i would be happy if this helps u. bye ... ...	sandip gaikwad sandy283792000	Dec 10, 2003 1:01 pm
214	ASSALAM O ALAIKUM TO ALL Is there any replacement for leonardo spectrum. plz mail me some useful softwares in this regard USMAN HAI ... Do you Yahoo!? ...	Usman Hai u_hai_30	Dec 15, 2003 6:36 pm
215	hello there, Can any body suggest me which sorting algorithm should i use for sorting a 128 elements array (8 bit n 2's complement) from HDL( verilog) point of...	Faisal Mahmood faysal_m	Dec 18, 2003 5:49 am
216	Hi Kannan, I do think i got a design for UART. IF you want i can mail it to u. Rao.Chinnam ... ...	chinnam maruthi rajeswari_l2001	Dec 18, 2003 7:48 pm
217	Hi friends My name is Krishna Kishore Balam and I am doing MS in electrical engineering. Hi kannan I also have one code for UART which works very fine. If you...	krishna kishore reddy... krishna_b_ki...	Dec 19, 2003 6:44 pm
218	hi, I think "systolic array" should help u in this regard. Ashwath ... __________________________________ Do you Yahoo!? New Yahoo! Photos - easier uploading...	Ashwath blashwath	Dec 22, 2003 3:47 am
219	hii guys!!! iam final yr engg student. i am doing my proj in vlsi.i want to know where i can get a synthesiser tool for code in verilog . i any body knows...	arun prasath chipbrain2003	Dec 22, 2003 10:01 am
220	hi Arun you can get synthesizer from Xilinx website. Xilinx ICE webpack is free for download. It is a good tool. bye KK ... hii guys!!! ... ...	krishna kishore reddy... krishna_b_ki...	Dec 22, 2003 3:15 pm
221	Hi Ashwath, Thanks for the 'algo' tip. It would be great if you could send me some more info about this 'Systolic Insertion algo'.As i could not find any...	Faisal Mahmood faysal_m	Dec 23, 2003 5:16 am
222	hi faisal, It has been long time i worked on algos, at the moment i dont have any material also. I think in web there are good "Implementaion Notes". Not only ...	Ashwath blashwath	Dec 23, 2003 5:55 am
223	hi guys, I am aware that synthesis tools are intelligent enough to optimize a state machine.Can any of the Synthesis tools detect the Deadlock states in the ...	Ashwath blashwath	Dec 23, 2003 3:58 pm
224	I want join ur yahoo group because I doing study on how to write verilog code for state machnine. Regard CPK1023 ... __________________________________ Do you...	camaron kitiara cpk1023	Dec 25, 2003 4:35 am
225	hi.. iam a new member in this group...iam designing a DSP processor in my research work...i need help in writing the verilog code for RAM... 4k *16 bit RAM...	praveen_verilog	Dec 26, 2003 9:44 am
226	Hi praveen.... This is Chintamani !!! Here is a code for a BUS steering logic for ISA card . This code was written in ModelSim and also works on Synopsys tool...	Chintamani Lonkar mani_bond007	Dec 28, 2003 3:07 am
227	Hello everybody! I need to output 2 elements ( 8 bit each) out of 128 element Data memory EVERY clock cycle.Any suggestion (ASAP) for this is welcome! Regards...	Faisal Mahmood faysal_m	Dec 29, 2003 5:34 am
228	put 128X2 byte FIFO which from which you can get 2 bytes at a clock and 128 byte data. -Nevil ... memory EVERY clock cycle.Any suggestion (ASAP) for this is...	Nevil Gajera nevilin2001	Jan 2, 2004 3:59 pm
229	Hi all, ia m looking for abreak in VLSI design please help,i am fresher Ramesh Nevil Gajera <nevilin2001@...> wrote: put 128X2 byte FIFO which from which...	ramesh s ramesh29_99	Jan 3, 2004 12:04 pm
230	hi... i need help in writing the testbench in verilog...actually iam simulating verilog programs using NC-launch cadence systems...here iam getting errors...	praveen_verilog	Jan 5, 2004 2:00 am
231	I think for test bench 'inout' should be declared as net(wire) while the output of test bench is ALWAYS wire.While for 'input' variables can be declared as...	Faisal Mahmood faysal_m	Jan 7, 2004 6:07 am
232	hi, Dont declare anything - it works fine - just port declaration is sufficient. Rgds Ashwath ... __________________________________ Do you Yahoo!? Yahoo!...	Ashwath blashwath	Jan 7, 2004 8:58 am
233	Note: the inout variable is a wire in both and testbench and the main program.u can chk the grops archives as i i had sent an example of Bus steering logic for...	Chintamani Lonkar mani_bond007	Jan 7, 2004 6:58 pm

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