put 128X2 byte FIFO which from which you can get 2 bytes at a clock and 128 byte data. -Nevil ... memory EVERY clock cycle.Any suggestion (ASAP) for this is...
Hi all, ia m looking for abreak in VLSI design please help,i am fresher Ramesh Nevil Gajera <nevilin2001@...> wrote: put 128X2 byte FIFO which from which...
hi... i need help in writing the testbench in verilog...actually iam simulating verilog programs using NC-launch cadence systems...here iam getting errors...
I think for test bench 'inout' should be declared as net(wire) while the output of test bench is ALWAYS wire.While for 'input' variables can be declared as...
hi, Dont declare anything - it works fine - just port declaration is sufficient. Rgds Ashwath ... __________________________________ Do you Yahoo!? Yahoo!...
Note: the inout variable is a wire in both and testbench and the main program.u can chk the grops archives as i i had sent an example of Bus steering logic for...
Hi, Can anyone suggest me some good book or ebook for synthesis with verilog? If you know some site where I can find tutorial on the same topic will also be...
Try Verilog HDL by Samir Palnitkar ... ===== ===== "WHEN HARDWORK AND PASSION ARE COMBINED, EXPECT A MASTER PIECE." __________________________________ Do you...
Snehal... U cud try Verilog synthesis book by Bhasker...I have also used the book by Ken Coffman and Michael Ciletti for advanced course in Verilog Synthesis. ...
Bhaskars book is really good Shristi S. ----Original Message Follows---- From: "rsnehal" Reply-To: verilog@yahoogroups.com To: verilog@yahoogroups.com Subject:...
Hi, I am a master's student studing in USA. I shall be graduating in the comming August and I plan to return to India soon after graduation. I know that the...
Hi shristi This is Chintamani. I am also a graduate student at Cal State Sacramento University and am doing my Masters in Electrical with specialization with...
hi snehal,, i feel "samir palnitker" is a good book for verilogHDL synthesis.. TRY IT,,,,, rsnehal <rsnehal@...> wrote: Hi, Can anyone suggest me some...
how to design a CLOCK using any basic digital gates and the design should not have any PLL or OSILATORS or other than gates.....??? plz let me know any of u...
U can use not gate !! If u connect the output of not gate to its input and use odd number of not gates lets say three then by application of a momentary pulse...
dear members i am new to group. i wnt wrire vhdl code for counter. entity is entity bi_counter is port (data : inout std_logic_vector(3 downto 0); ...
ramaraju.elec
ramaraju.elec@...
Feb 25, 2004 12:12 pm
245
here is the sol to a simmilar problem..hope it helps.. Design a 4-bit counter (count up) with enable and load. The reset is an asynchronous reset and active...
hi, can we implement trransmission gate in FPGA using VHDL code. if so please explain. how. i know it can be done using IO buffers of fpga. say suppose i wanna...
ramaraju.elec
ramaraju.elec@...
Feb 26, 2004 6:56 am
247
Hi Shrivastava, i am very much thakful for your reply. Here problem is with bi-directional bus. When load=1 bus has to become as input. If count_en=1 then bus...
ramaraju.elec
ramaraju.elec@...
Feb 26, 2004 8:53 am
248
Hi all.. I am thankful to all you guys, who have been very prompt and diligently replied to my queries on MOS Physics. Thanks to you guys, i could ask you some...
Check out this link !! http://www.geocities.com/deepakgeorge2000/fifo.htm ... ===== ===== "WHEN HARDWORK AND PASSION ARE COMBINED, EXPECT A MASTER PIECE." ...
whats the problem??? Sriram rsnehal <rsnehal@...> wrote: Hi guys, I am havig some problem with cadence PKS tool...can any one please help me with it? ......
oh thanx a lot for replying... well it might be a stupid problem...i tried synthesising my verilog code using PKS it did got synthesised now when i tried to...
Hello Everybody I have to design and implement a microcontroller on FPGA in verilog . Could anyone please tell me any good referance for microprograming or...
hi everyone......I am doing verilog in university these days...I have to submitt a project proposal...I need to know (want a suggestion)...that what should I...
Basics of verilog !! www.deeps.org ... ===== ================================== Chintamani Lonkar MS Electrical Engineering California State University...
Basics of verilog !! www.deeps.org ... ===== ================================== Chintamani Lonkar MS Electrical Engineering California State University...
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