Hello, I m trying to design ROM (no particulars) using verilog. Can any one provide me its code for study. regards. USMAN HAI ... Do you Yahoo!? Win a $20,000...
dear all, I have to develop a bubblesort embedded system that will run on a VIRTEX-II Microblaze Development Kit board. This system must prompt the user via...
HIII.. DESIGNING ROM IS SIMPLE.JUST U DESIGN A ARRAY WHOSE DEPTH DEPENDS ON THE MEMORY CAPACITY. GOODBYE ... Do you Yahoo!? Win a $20,000 Career Makeover at...
HII GUYS I AM FRESHER JUST FINISHED MY ENGG IN ECE. CAN ANY OF U GUIDE ME TO SELECT A COLLEGE TO PROCEED MY HIGHER STUIDIES IN VLSI IN INDIA... Usman Hai...
Hi, CAN ANY ONE PROVIDE SIMPLEST SOLUTION OF DESIGNING NUMERIC CONTROLL OSCILLATOR ON FPGA. ITS BASICALLY DSP RELATED. THANKS USMAN HAI ... Do you Yahoo!? ...
hi all, i'm first time taking the verilog course. and have the project which is release candy @ 35c and return 15c in nickel only if 50c is entered. How can i...
HI all...can anybody explain me how to design verilog hardware for mapping memory . I have a 16-bit bus to be which is to be mapped to different registers and...
HI all...can anybody explain me how to design verilog/vhdl hardware for mapping memory . I have a 16-bit bus to be which is to be mapped to different registers...
First try defining a state machine, and identify your signals. I would assume you have such signals as clock, coin_value_x1_paid, coin_value_x2_paid,...., and...
hii ,, i am fresh graduate. i want to join master degree in vlsi. can any body help me to choose good universities in india. Yahoo! India Matrimony: Find your...
Hi all I am having a trouble with one of the verilogXl netlisting options(Generate PinMap option).. this option is not generating the right pinmap ... I will...
hi, i m doing MTech. in "MICROELECTRONICS" at IIT bombay. For VLSI it's a really good institute to be in, also staff here is quite good. On that, placements...
Dear Friends, I am very thankful, If any one have any idea or have a material on FIR comb, FIR low pass, FIR Notch filter design. I am very greatful to you if...
hello everyone can anyone help me in desiging the 4 bit adder & multiplier on verilog i will be very thankful to u guys waiting for ur reply Win a Gillette...
hello, what kind of help exactly do u want ? for adder, first u just write code for single bit and then use that module 4 times. u'll have 5 inputs (4 bits and...
Synopsys is Hiring for Hyderabad center, people having experience with 1-5 years of experience in DFT, Analog Simulation, Physical Design, Layout, Physical...
Synopsys is Hiring for Hyderabad center, people having experience with 1-5 years of experience in DFT, Analog Simulation, Physical Design, Layout, Physical...
Hi go to www.opencores.com u can find UART Satish Sujatha s <sujatha6621@...> wrote: Dear all, Could any one please tell me where can i get the VHDL...
Dear All, One of the leading MNC located in Bangalore, Karnataka is looking candidates for the following Positions: 1) Position: Sr. Engineer/ Team Lead Exp:...
Hi all.. A very basic doubt on inverter chaining... given a chain of inverters and the propagation delay.. how do we determine the setup and hold time.....
I am Ebad Ullah from NED university. My final year project is implementation of Ethernet switch on Xilinx FPGA.If anybody can help me in this aspect mail me . ...
I am a recruiter exclusively for the EDA start up community. This is a position that I am seeking candidates for today. I do have several other EDA Jobs as...
Please answer this question how could one can write a programme for modulation in Verilog waiting for reply. modulation: is mixing a low frequency signal with...
I'm sure there are other ways to do that, but what about combining the output of clock dividers? for instance: module x ( //input clock //output mod_signal ) ...
Depends on what type of modulation, for amplitude modulation with logic clock signals a simple AND gate would work. Regards, Trampas ... From: sruthiteja...
Dear friends, Please do needful help for the below problem. The following code is working perfectly for simulation but i am worrying about synthesis. so please...
Dear friends, Please do needful help for the below problem. The following code is working perfectly for simulation but i am worrying about synthesis. so please...
Satish, I think if u look at the last combo block u will find a latch being inferred in the statement " else cph1_reg = cph1_reg; end " as in combo logic u...
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