Hi all.. A very basic doubt on inverter chaining... given a chain of inverters and the propagation delay.. how do we determine the setup and hold time.....
I am Ebad Ullah from NED university. My final year project is implementation of Ethernet switch on Xilinx FPGA.If anybody can help me in this aspect mail me . ...
I am a recruiter exclusively for the EDA start up community. This is a position that I am seeking candidates for today. I do have several other EDA Jobs as...
Please answer this question how could one can write a programme for modulation in Verilog waiting for reply. modulation: is mixing a low frequency signal with...
I'm sure there are other ways to do that, but what about combining the output of clock dividers? for instance: module x ( //input clock //output mod_signal ) ...
Depends on what type of modulation, for amplitude modulation with logic clock signals a simple AND gate would work. Regards, Trampas ... From: sruthiteja...
Dear friends, Please do needful help for the below problem. The following code is working perfectly for simulation but i am worrying about synthesis. so please...
Dear friends, Please do needful help for the below problem. The following code is working perfectly for simulation but i am worrying about synthesis. so please...
Satish, I think if u look at the last combo block u will find a latch being inferred in the statement " else cph1_reg = cph1_reg; end " as in combo logic u...
karam
karamveer.yadav@...
Jul 8, 2004 6:11 am
309
Hi All...... One of our client is very urgently looking for the following Position: Position: Project Lead/ Manager- Applications Engineering Job Location:...
Satish, What you can possibly do is don't include the else staatement. Only if you have a condition true, you are going to update it. If you don't use else, it...
Hi Kiran, Thank you for the reply...if i remove else statement also the tool giving problem...i changed the logic as the tool supports now its fine but still i...
dear ebad u can contact DR.Usman ali shah in ur electronics dept. hez a very intellegent and genius teacher in the history of vLSI if u hve any prob then...
Hi Satish: Actually it is coding style problem, In one case it causes logical feedback loopback and also in second case it is generating LATCH. Both are not...
Dear All, One of our leading MNC client is looking for following Candidates. Position: Hardware Verification Engineer Exp: 2- 4 years Job LOcation: Bangalore ...
Dear All, We are Looking for the following Positions for a Leading MNC client. 1) Position: Physical Design Job Location: Bangalore Exp: 3-9yrs Skills: ASIC /...
Hi everyone, I need to know from where can i get VHDL for Linux/Windows. I know this is a verilog group, but even though anybody if having some information...
Hi An world leader in Memory Chip Design is seeking a PCI Express Professional for their Bangalore Operations Key Skills: 1. Strong knowledge PCI-Express ...
Hi, We would like to convey you that we have requirement for Hardware Designers with 4+yrs of experience for our client in Hyderabad. So if you are interested,...
Hello I am a fresh graduate with Master's of Engineering in Microelectronics. I am willing to relocate i India(Delhi). Please review my resume and inform me...
Hi All..... One of our Leading MNC Client in Bangalore is Looking for Design Verification Engineers ---- immediate Opening.. Position: Design Verification Job...
IEDCS'04 -1st International Electronics Design Contest for Students www.handasa-arabia.org/iedcs04 Handasa Arabia (www.handasarabia.org), University of...
http://www.handasarabia.org/document.php?id=152 Research is crucial for development. There is a requirment for aggregation of distrubuted intellectual research...
Hi. Our client, a leading American Company, world's number one provider of FPGA synthesis solutions, serving approximately 43,000 customers worldwide is...
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