verilog : Messages : 325-356 of 735

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325	New EDA Jobs group...	email me johndeeres1	Sep 1, 2004 4:00 pm
326	http://www.handasarabia.org/document.php?id=152 Research is crucial for development. There is a requirment for aggregation of distrubuted intellectual research...	Mohamed Salem mosalem2003	Sep 12, 2004 10:54 am
327	Hi there; can any one tell me how can I convert a file in .blif format to verilog-XL format? regards snehal...	rsnehal	Sep 21, 2004 8:22 pm
328	Hi. Our client, a leading American Company, world's number one provider of FPGA synthesis solutions, serving approximately 43,000 customers worldwide is...	alphaeus_embedded alphaeus_emb...	Sep 28, 2004 3:21 am
329	Hi, I am new using verilog, I would like to know how to compile and simulate a code. Is it necessary to include libraries like in VHDL? ...	MAURICIO VELASQUEZ evilmao2002	Sep 30, 2004 1:35 pm
330	i think u need to ask some elaborate question, i mean what tool r u using, etc. kaushal verilog@yahoogroups.com wrote: Message: 1 Date: Thu, 30 Sep 2004...	Kaushal Patel kaushalkumar...	Oct 1, 2004 8:14 pm
331	Hello, Well, now I am using Debian (a Linux OS), and I downloaded a tool called Icarus Verilog. I really don't know how to use it but I am trying to understand...	evilmao2002	Oct 2, 2004 2:19 am
332	Hi Go to www.xilinx.com and download Modelsim XE 5.7(Free Version) and it is very user friendly. evilmao2002 <evilmao2002@...> wrote: Hello, Well, now I...	Dheeraj kr. dheeraj_1978	Oct 2, 2004 4:43 am
333	Hi, thanks for answering me. There is a big problem with the tool Modelsim: It is not free software and I work in an organization that promotes the use of free...	evilmao2002	Oct 2, 2004 5:21 pm
334	Hi I'd suggest first consulting a good book and reading through few chapters before diving into verilog. It is, at some corners, VERY different from VHDL and ...	Akhilesh Mritunjai virtualaspirin	Oct 2, 2004 6:53 pm
335	hi evilmao2002, try the following tutorial. its a nice tutorial to start learning verilog. and its in very simple language for beginners. ...	Kaushal Patel kaushalkumar...	Oct 2, 2004 7:03 pm
336	Thanks for your collaboration, I will read the tutorial and read the introduction of the page www.vol.webnexus.com....	evilmao2002	Oct 2, 2004 8:45 pm
337	HI ALL, There are some exciting VLSI openings in Bangalore. These are openings with TOP companies and such salary is not an issue. Find Details of the...	singhsagarsk	Oct 6, 2004 11:11 am
338	Hi All, I am a new member of this group.I have one doubt in verilog coding. Is it possible to append the data, if we are using system tasks like $fdisplay, to...	K.V.S.SREENIVASAN vasan_coep	Oct 6, 2004 2:35 pm
339	singhsagarsk <singhsagarsk@...> wrote: HI ALL, There are some exciting VLSI openings in Bangalore. These are openings with TOP companies and such salary...	keyur halari sofi_andros2k	Oct 6, 2004 3:49 pm
340	Hello Mr keyur halari whats the point to send to evryone, just send to the concern. Its a humble request to all members to refrain from this kind of act. ...	Afzal Ahmad USMANI Usmani.AFZAL@...	Oct 6, 2004 3:59 pm
341	Hi All, Please find a Urgent requirement. Experience 5 -8 yrs Candidate should have handled a team lead / tech lead role. Role: Technical lead for Xilinx...	singhsagarsk	Oct 12, 2004 12:12 pm
342	Hi, Does anybody know how to inject noise into one or more input signals of the verilog design during modelsim simulation? Thank you very much for your help. ...	lobowang	Oct 22, 2004 6:46 pm
343	Hi, We have an excellent opportunity for you with one of our MNC clients. They are world's number one provider of FGPA synthesis solutions, serving...	alphaeus_embedded alphaeus_emb...	Oct 25, 2004 4:24 pm
344	Hi Everyone Texas Instruments India is organizing TI Developer's conference on 1st and 2nd December in Bangalore. The TI Developer Conference has more than 50...	deosiddharth	Nov 17, 2004 5:56 pm
345	Hi everyone, I have been a silent member of this group till now but I have followed the post to this group regularly. I am currently working on design of IP...	deosiddharth	Nov 17, 2004 6:05 pm
346	Hi, They're are loads of risc cores on opencores.org. Some of those should be of help...	Daniel Larkin totallychips	Nov 17, 2004 6:06 pm
347	Hi Siddarth, I have worked on development of 8-bit RISC processor (Microchip's PIC16C57X). We developed this core starting from scratch. You can find the some...	vamsi kalyan vamsi_2102001	Nov 18, 2004 4:11 am
349	Hi, I need a verilog program that will copy contents from say a 5 x 10 static memory rom (or ram) and write to a static ram of size 10 x 10 upon enable. How...	Helix vex_helix	Nov 20, 2004 2:16 am
350	Hi! Hope someone could help me to point to me where I might have gone wrong in designing this simple ROM verilog code. There are three modules involved here. i...	Gary Simon garysimon_jr	Nov 22, 2004 11:10 am
351	hai gays to carry out research on verilog and to find solutions of your problems join the group verilog_uet __________________________________ Do you Yahoo!? ...	hassan Bhatti hassan39_2001	Nov 22, 2004 2:16 pm
352	hai girls and guys to carry out research on verilog and to find solutions of your problems join the group verilog_uet __________________________________ Do you...	hassan Bhatti hassan39_2001	Nov 22, 2004 2:16 pm
353	Hi Gary!! You have not declared ROM_data in test_ROM1 module. Vamsi ... ________________________________________________________________________ Yahoo!...	vamsi kalyan vamsi_2102001	Nov 23, 2004 5:46 am
354	Helix, I am sending a part of Verilog code. May be it is helpful for you. parameter depth=10; if(enable) begin for(i=0;i<depth;i=i+1) ...	vamsi kalyan vamsi_2102001	Nov 23, 2004 5:51 am
356	hi all what is racing condition in verilog? why racing condition arise when same varilog code run in different simulator? expain briefly about the racing...	mullai malli mullai_kurunchi	Nov 29, 2004 8:38 am

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