i think u need to ask some elaborate question, i mean what tool r u using, etc. kaushal verilog@yahoogroups.com wrote: Message: 1 Date: Thu, 30 Sep 2004...
Hello, Well, now I am using Debian (a Linux OS), and I downloaded a tool called Icarus Verilog. I really don't know how to use it but I am trying to understand...
Hi Go to www.xilinx.com and download Modelsim XE 5.7(Free Version) and it is very user friendly. evilmao2002 <evilmao2002@...> wrote: Hello, Well, now I...
Hi, thanks for answering me. There is a big problem with the tool Modelsim: It is not free software and I work in an organization that promotes the use of free...
Hi I'd suggest first consulting a good book and reading through few chapters before diving into verilog. It is, at some corners, VERY different from VHDL and ...
HI ALL, There are some exciting VLSI openings in Bangalore. These are openings with TOP companies and such salary is not an issue. Find Details of the...
Hi All, I am a new member of this group.I have one doubt in verilog coding. Is it possible to append the data, if we are using system tasks like $fdisplay, to...
singhsagarsk <singhsagarsk@...> wrote: HI ALL, There are some exciting VLSI openings in Bangalore. These are openings with TOP companies and such salary...
Hello Mr keyur halari whats the point to send to evryone, just send to the concern. Its a humble request to all members to refrain from this kind of act. ...
Afzal Ahmad USMANI
Usmani.AFZAL@...
Oct 6, 2004 3:59 pm
341
Hi All, Please find a Urgent requirement. Experience 5 -8 yrs Candidate should have handled a team lead / tech lead role. Role: Technical lead for Xilinx...
Hi, Does anybody know how to inject noise into one or more input signals of the verilog design during modelsim simulation? Thank you very much for your help. ...
Hi Everyone Texas Instruments India is organizing TI Developer's conference on 1st and 2nd December in Bangalore. The TI Developer Conference has more than 50...
Hi everyone, I have been a silent member of this group till now but I have followed the post to this group regularly. I am currently working on design of IP...
Hi Siddarth, I have worked on development of 8-bit RISC processor (Microchip's PIC16C57X). We developed this core starting from scratch. You can find the some...
Hi, I need a verilog program that will copy contents from say a 5 x 10 static memory rom (or ram) and write to a static ram of size 10 x 10 upon enable. How...
Hi! Hope someone could help me to point to me where I might have gone wrong in designing this simple ROM verilog code. There are three modules involved here. i...
hai gays to carry out research on verilog and to find solutions of your problems join the group verilog_uet __________________________________ Do you Yahoo!? ...
hai girls and guys to carry out research on verilog and to find solutions of your problems join the group verilog_uet __________________________________ Do you...
Hi Gary!! You have not declared ROM_data in test_ROM1 module. Vamsi ... ________________________________________________________________________ Yahoo!...
hi all what is racing condition in verilog? why racing condition arise when same varilog code run in different simulator? expain briefly about the racing...
Hi Racing Conditioon occoryus when setup time of flip flops are violated....Well you muust use non - blocking assignment stratement in your code to make it...
hi can anyone tell difference between 2 different mux coding style . Design a 4:1 mux in Verilog. Multiple styles of coding. e.g. Using if-else statements ...
If some body can give more good answers i will be thankful to him. ... Well, i does not know abt this very much if there is some exceptional difference except...
hi sir, thanks for the reply.I wanted to work on parametrised,reuseble and configurable IP core of a risc controller for soc independent of any technology...
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