verilog : Messages : 344-375 of 735

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344	Hi Everyone Texas Instruments India is organizing TI Developer's conference on 1st and 2nd December in Bangalore. The TI Developer Conference has more than 50...	deosiddharth	Nov 17, 2004 5:56 pm
345	Hi everyone, I have been a silent member of this group till now but I have followed the post to this group regularly. I am currently working on design of IP...	deosiddharth	Nov 17, 2004 6:05 pm
346	Hi, They're are loads of risc cores on opencores.org. Some of those should be of help...	Daniel Larkin totallychips	Nov 17, 2004 6:06 pm
347	Hi Siddarth, I have worked on development of 8-bit RISC processor (Microchip's PIC16C57X). We developed this core starting from scratch. You can find the some...	vamsi kalyan vamsi_2102001	Nov 18, 2004 4:11 am
349	Hi, I need a verilog program that will copy contents from say a 5 x 10 static memory rom (or ram) and write to a static ram of size 10 x 10 upon enable. How...	Helix vex_helix	Nov 20, 2004 2:16 am
350	Hi! Hope someone could help me to point to me where I might have gone wrong in designing this simple ROM verilog code. There are three modules involved here. i...	Gary Simon garysimon_jr	Nov 22, 2004 11:10 am
351	hai gays to carry out research on verilog and to find solutions of your problems join the group verilog_uet __________________________________ Do you Yahoo!? ...	hassan Bhatti hassan39_2001	Nov 22, 2004 2:16 pm
352	hai girls and guys to carry out research on verilog and to find solutions of your problems join the group verilog_uet __________________________________ Do you...	hassan Bhatti hassan39_2001	Nov 22, 2004 2:16 pm
353	Hi Gary!! You have not declared ROM_data in test_ROM1 module. Vamsi ... ________________________________________________________________________ Yahoo!...	vamsi kalyan vamsi_2102001	Nov 23, 2004 5:46 am
354	Helix, I am sending a part of Verilog code. May be it is helpful for you. parameter depth=10; if(enable) begin for(i=0;i<depth;i=i+1) ...	vamsi kalyan vamsi_2102001	Nov 23, 2004 5:51 am
356	hi all what is racing condition in verilog? why racing condition arise when same varilog code run in different simulator? expain briefly about the racing...	mullai malli mullai_kurunchi	Nov 29, 2004 8:38 am
357	Hi Racing Conditioon occoryus when setup time of flip flops are violated....Well you muust use non - blocking assignment stratement in your code to make it...	Dheeraj kr. dheeraj_1978	Nov 30, 2004 11:18 am
358	hi can anyone tell difference between 2 different mux coding style . Design a 4:1 mux in Verilog. Multiple styles of coding. e.g. Using if-else statements ...	jigar5234	Dec 4, 2004 10:48 am
359	If some body can give more good answers i will be thankful to him. ... Well, i does not know abt this very much if there is some exceptional difference except...	hassan Bhatti hassan39_2001	Dec 6, 2004 9:08 pm
360	Hello, The link to this paper talks about coding style for improved simulation efficiency: ...	Jonny Miller the_deer_chaser	Dec 6, 2004 9:49 pm
361	hi sir, thanks for the reply.I wanted to work on parametrised,reuseble and configurable IP core of a risc controller for soc independent of any technology...	siddharth deo deosiddharth	Dec 11, 2004 1:16 pm
362	hi sir, thanks for the reply.I wanted to work on parametrised,reuseble and configurable IP core of a risc controller for soc independent of any technology...	siddharth deo deosiddharth	Dec 11, 2004 1:17 pm
363	hi sir, thanks for the reply.I wanted to work on parametrised,reuseble and configurable IP core of a risc controller for soc independent of any technology ...	siddharth deo deosiddharth	Dec 11, 2004 2:16 pm
364	hi all explain how to compile vpi module using icarus tool?how to invoke pli interface in verilog code using icarus tool.i installed icarus tool.i didn't get...	mullai malli mullai_kurunchi	Dec 16, 2004 1:32 pm
365	Hai, How to generate a ASIC gate count of a verilog design project using Xilinx ISE Webpack. If the webpack does not generate ASIC gate count, what are the...	Dattatreya Reddy dattudotcom	Dec 19, 2004 9:16 pm
366	hi everyone, I needed help to zero down on my masters project topic.I wanted to work on an IP for RISC enhancement .I started with IP core of a risc ...	deosiddharth	Dec 22, 2004 6:19 am
367	????? ?:"deosiddharth"<deosiddharth@...> ... ?:2004?12?22??????2:17? ??:[verilog]ip???? ????, ?????????????????.???????? ??RISC????IP????.???risc?IP?????...	lllh1 lllh1@...	Dec 22, 2004 1:36 pm
368	Hi, Our client, a TOP MNC having Forty of the Fortune 100, including ABN AMRO, BMW, Chevron, Cisco Systems, Hewlett-Packard, Unilever�. is seeking top-notch...	alphaeus_embedded alphaeus_emb...	Dec 30, 2004 2:33 pm
369	hi everyone, I am implementing a decicated processor for converting IPv4 packets to IPv6 packets and vice versa.Can you suggest some refrences (books,research...	deosiddharth	Jan 3, 2005 9:19 am
370	Hello sir. As you had suggested I am implementing a decicated processor for converting IPv4 packets to IPv6 packets and vice versa.Can you suggest some ...	siddharth deo deosiddharth	Jan 3, 2005 9:37 am
371	????? ?:"deosiddharth"<deosiddharth@...> ... ?:2005?1?03??????5:19? ??:[verilog]????(?IPv4????IPv6?,?????????)...	lllh1 lllh1@...	Jan 3, 2005 4:17 pm
372	... From: "siddharth deo" <deosiddharth@...> To: <verilog@yahoogroups.com> Sent: Monday, January 03, 2005 5:37 PM Subject: Re: [verilog] IP core of RISC...	lllh1 lllh1@...	Jan 3, 2005 4:19 pm
373	... From: "lllh1" <lllh1@...> To: <verilog@yahoogroups.com> Sent: Tuesday, January 04, 2005 12:19 AM Subject: Re: [verilog] IP core of RISC Controller...	lllh1 lllh1@...	Jan 4, 2005 4:24 pm
374	... From: "lllh1" <lllh1@...> To: <verilog@yahoogroups.com> Sent: Tuesday, January 04, 2005 12:17 AM Subject: Re: [verilog] Project Topic(IPv6 packet to...	lllh1 lllh1@...	Jan 4, 2005 4:56 pm
375	... From: "lllh1" <lllh1@...> To: <verilog@yahoogroups.com> Sent: Tuesday, January 04, 2005 12:19 AM Subject: Re: [verilog] IP core of RISC Controller...	lllh1 lllh1@...	Jan 4, 2005 5:55 pm

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