hi everyone, I have some questions w.r.t soc design flow using reuseble processor core. -How do we Integrate a hardware acclerator to a processor core I am...
hi everyone, I have a set of very useful projects drawn from the ieee transections on vlsi.Anyone intersted and needs a project topic for there masters or is...
Hi everyone, Many people seem to be looking form razavi,Gray and Mayers solutions.I have solved a significant portion of razavi as the part of Graduate ...
hi everyone, I uploaded two documents that containg list of papers from IEEE transections on VLSI and IEEE transections on computers under the name ieee...
hi everyone, I needed some refrences(books,websites,papers) for writing efficient verilog codes.I done verilog from phalnitkar,basically i needed tips for...
Hi, A world leader in EDA ad IP Design Technology is seeking top-notch software professionals strong in C/C++ and Unix with over 7 years of experience in...
Hi, A world leader in EDA ad IP Design Technology is seeking top-notch software professionals strong in C/C++ and Unix with over 7 years of experience in...
Hello! I am new in verilog design and i have to project for school a CROM (Control ROM) simulation in verilog. Please could somebody help me with lines. Thank...
Hi everyone, Can any one help me with bus interface logic.I have to code a 32 bit bidirectional bus and its interface with bidirectional shift registers which...
Hi all, What is the difference between VHPI and FLI?...I am doing project in vhdl...Currently i am using ModelSim Se simulator..Is MoselSim Se support both...
Hi all, What is the difference between VHPI and FLI?...I am doing project in vhdl...Currently i am using ModelSim Se simulator..Is MoselSim Se support both...
hi everyone, I have downloaded nnARM core from http://www.foo.be/docs/nnARM/,but the core is not synthesizeble on RC compiler.Has anyone synthesized this core....
Hi, Client: A World leader in EDA and IP Design Technology. Location: Bangalore. Experience: 6 to 8 years. Education: Professional B.E/B.Tech (CS/Electronics)....
hi groups can u help me to do project in fpga such as designing of any fpga functionality or from where i can get fpga based project,in which i can implement...
Hello all, Can someone suggest me a place where i can get the Verilog RTL code of an 8 - Bit Galois Field Multiplier (GF). I need it for my project. The one...
Hi all, It's me again. Please go through this link for the 8 bit GF Multiplier. http://bw-www.ie.u-ryukyu.ac.jp/~wada/design04/spec_e.html I was able to code...
Opening for ASIC Front End Designer in Kuala Lumpur, Malaysia. Hi, We have immediate requirements for ASIC Front End Designer on Contract for our client in...
Hi, A world leader in EDA ad IP Design Technology is seeking top-notch software professionals strong in C/C++ and Unix with 2 to 6 years of experience in...
hi everyone, Anyone worked on or is working on image compression using EZW(embedded zero wavelet tree). I am trying to implement it using hdl regards Siddharth...
Hello Guys, Good Day! I have been following questions and posts on this verilog users group. I am writing to express my interest in Design (ASIC/ CMOS/ VLSI)...
hello all i am newmember of this group. I am a fresher. can any one give me some good verilog examples. Also if u Upload some good documents on verilog to...
Hi, I need to check the signal voltage value for a signal. How can we do in verilog. Is this possible in verilog, if so how can we do. And if we can not in...
... in verilog. Is this possible in verilog, if so how can we do. And if we can not in verilog how do I can do this in another HDL or other languages. ... Not...
Hello, In Verilog you can only work with High or Low signal values. You can work in Verilog AMS or Pspice. bye Sridhar ... in verilog. Is this possible in...
Hi, I am using Verilog for verification. I would like to use internal signals of DUT in a testcase. can we access or if not how do we do. Hope for an immediate...
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