Hi, Client: A World leader in EDA and IP Design Technology. Location: Bangalore. Experience: 6 to 8 years. Education: Professional B.E/B.Tech (CS/Electronics)....
hi groups can u help me to do project in fpga such as designing of any fpga functionality or from where i can get fpga based project,in which i can implement...
Hello all, Can someone suggest me a place where i can get the Verilog RTL code of an 8 - Bit Galois Field Multiplier (GF). I need it for my project. The one...
Hi all, It's me again. Please go through this link for the 8 bit GF Multiplier. http://bw-www.ie.u-ryukyu.ac.jp/~wada/design04/spec_e.html I was able to code...
Opening for ASIC Front End Designer in Kuala Lumpur, Malaysia. Hi, We have immediate requirements for ASIC Front End Designer on Contract for our client in...
Hi, A world leader in EDA ad IP Design Technology is seeking top-notch software professionals strong in C/C++ and Unix with 2 to 6 years of experience in...
hi everyone, Anyone worked on or is working on image compression using EZW(embedded zero wavelet tree). I am trying to implement it using hdl regards Siddharth...
Hello Guys, Good Day! I have been following questions and posts on this verilog users group. I am writing to express my interest in Design (ASIC/ CMOS/ VLSI)...
hello all i am newmember of this group. I am a fresher. can any one give me some good verilog examples. Also if u Upload some good documents on verilog to...
Hi, I need to check the signal voltage value for a signal. How can we do in verilog. Is this possible in verilog, if so how can we do. And if we can not in...
... in verilog. Is this possible in verilog, if so how can we do. And if we can not in verilog how do I can do this in another HDL or other languages. ... Not...
Hello, In Verilog you can only work with High or Low signal values. You can work in Verilog AMS or Pspice. bye Sridhar ... in verilog. Is this possible in...
Hi, I am using Verilog for verification. I would like to use internal signals of DUT in a testcase. can we access or if not how do we do. Hope for an immediate...
well i'm a novice in field of verilog can any one suggest me how to start with it verilog@yahoogroups.com wrote: There is 1 message in this issue. Topics in...
hi, Syntax wise you can access it. But it is not good practise to do that for verification(your env will not be useful for netlist verification). For applying ...
hi everyone, Can anyone suggest some refrence that discusses hdl implementation of control unit using state machine.I have a set of fifteen instructions for...
Hi! Nested case statements are doable. No probs. It will synthesize as multiple muxex in series. (hoping that you'll use them in combinatination logic) ...
Hi. Joined verilog group just now. I am a recent graduate from Dallas. I've been searching for jobs in Analog for a while now, but was not able to get into it,...
Thanks to siddharth, I selected a nice project of Audio FIR filter design. Now can I use any avalable cores to implement relatively complex project and later...
Thanks to siddharth, I selected a nice project of Audio FIR filter design. Now can I use any avalable cores to implement relatively complex project and later...
Blank Hi Friends, Can anybody mail me stuff regarding 1) Description on State Machines in digital design!! 2) Explanations on coding styles of state machines...
Vipul
vipul@...
Apr 25, 2005 6:07 am
448
Hi All; Can anybody tell me the difference in `DEFINE and PARAMETER. thanks vikas __________________________________________________ Do You Yahoo!? Tired of...
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