Hi, I am using Verilog for verification. I would like to use internal signals of DUT in a testcase. can we access or if not how do we do. Hope for an immediate...
well i'm a novice in field of verilog can any one suggest me how to start with it verilog@yahoogroups.com wrote: There is 1 message in this issue. Topics in...
hi, Syntax wise you can access it. But it is not good practise to do that for verification(your env will not be useful for netlist verification). For applying ...
hi everyone, Can anyone suggest some refrence that discusses hdl implementation of control unit using state machine.I have a set of fifteen instructions for...
Hi! Nested case statements are doable. No probs. It will synthesize as multiple muxex in series. (hoping that you'll use them in combinatination logic) ...
Hi. Joined verilog group just now. I am a recent graduate from Dallas. I've been searching for jobs in Analog for a while now, but was not able to get into it,...
Thanks to siddharth, I selected a nice project of Audio FIR filter design. Now can I use any avalable cores to implement relatively complex project and later...
Thanks to siddharth, I selected a nice project of Audio FIR filter design. Now can I use any avalable cores to implement relatively complex project and later...
Blank Hi Friends, Can anybody mail me stuff regarding 1) Description on State Machines in digital design!! 2) Explanations on coding styles of state machines...
Vipul
vipul@...
Apr 25, 2005 6:07 am
448
Hi All; Can anybody tell me the difference in `DEFINE and PARAMETER. thanks vikas __________________________________________________ Do You Yahoo!? Tired of...
Hi, We use parameter & ‘define constructs in verilog to define constants. Parameters must be defined with in the module (i.e., they have scope with in the...
Hi Vikas, Parameter ======= Parameter are primarily to make the code more readable and easy to modify. They are declared and declared just once, usually near...
Hey Sirish, thanks for that nice explanation BUT I disagree with regard to ... only parameter can be changed at compile time Parameter is used to define...
Vipul
vipul@...
Apr 27, 2005 11:55 am
452
Hey Sirish, thanks for that nice explanation BUT I disagree with regard to ... only parameter can be changed at compile time Parameter is used to define...
Vipul
vipul@...
Apr 27, 2005 11:57 am
453
hi all, both are used to define constant define is used to define text macros The verilog compiler subsitutes the text of the macro where ever it encounters...
Vipul
vipul@...
Apr 27, 2005 12:29 pm
454
Things are really picking up in the high tech world! Currently I am seeking all types of engineers ranging from the EDA space and ASIC/CPU/SOC space. Please...
Hello Everybody, Thanks guys for a nice discussion on define and parameter. I hv one more doubt on using FORK - JOIN inside the other FORK - JOIN. Thanks ...
Hello Everybody, Thanks guys for a nice discussion on define and parameter. I hv one more doubt on using FORK - JOIN inside the other FORK - JOIN. Thanks ...
Hi vipul, hmm good work vipul, I appreciate ur effort. what I have observed in ur code is u r trying to pass the redefined value through instantiation. I...
Hi vikas,
ya u can do that , but use it only when u want a block of code to be executed in parallel at a particular simulation time(otherwise there is...
hello, i am looking for an efficient square root algorithm, i want to implement newton-raphson's square root algorithm and it will take for 150 cycle for a...
Hi! I am implementing a switch in Verilog capable of switching ATM packets. I would like ot know how to test the functionality of the switch? I know test bench...
we are working on a VHDL project and we've successfully completed place and route using Xilinx ISE Project Navigator. But I am getting error while using iMPACT...
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