hi friends, can anybody tell me what is $timeformat ?? & how to use it?? regards, vipul...
vipul@...
May 6, 2005 11:27 am
465
Hi Vipul I think it will help u, $timeformat(unit, precision, "suffix", min_field_width); Controls the format used by the %t text format specifier. unit is the...
Please i need someone's help pls i am working on a small project(ALU bit) and looking how to put in some simulation parameter in a verilog file before...
Hi , I'm new to using PLIs. I need to run a C- Testbench on a Verilog code. Could some one help me how to instantiate the Verilog module in my C- testbench? I...
Guys, I was reading thru the PLI literature and got to understand I'm taking a different (or wrong) approach of solving my problem. Let me rephrase my...
hi friends, i have a question regarding task if suppose a task has 3 inputs but i send only 2 inputs like task three_inputs; input one; input two; input three;...
vipul@...
May 13, 2005 11:51 am
470
hassan bhatti moderator verilog_uet@yahoogroups.com Uet Taxila ... u can call tasks of three inputs with only two in this way three_inputs(1'b0,1'b1,); this is...
Hi Vipul, It wont compile. It will tell you that you have passed less number of inputs than expected. And regarding recursion(calling the task again in the...
Mauricio Velazquez has invited you to join hi5. By joining hi5, you will be connected to Mauricio and all of Mauricio's friends. hi5 is the place where friends...
Hi Friends, I am working on TAP controller for boundary scan test. my question is regarding the boundary scan register, now what happens is when the Tap...
vipul@...
Jun 6, 2005 7:20 am
476
Hey ppl, I jus want to invert a 4 bit bus.. I used assign statement but ICARUS is giving Syntax error.. have tried all combo of syntax.. wire [3:0] bbar; ...
... You're using a non-blocking statement (<=), assign can only be used with a blocking statement (=) i.e. the following should work wire [3:0] bbar; assign...
Hi Aanjhan, Try assign bbar = !b; or assign bbar = ~b; Both will work. You are using non-blocking style for continous assignment. Thanks, Phani ... -- ... Pure...
Hi phani, i dont agree with ur point i.e.,(assign bbar = !b) in anju's case. this is a logical negation operator with result of 1 bit size. anju try (assign...
Hi Sirish, I do agree with you in his case. But I am not sure if we can use non-blocking statement for continous assignment. Thanks, Phani On 9 Jun 2005...
Hi phani,
we cannot use non-blocking assignment in continous assign statements,bcoz assign statements are concurrent i.e., assign statements execution...
Hi Sirish, Yes you are right. Infact simulator will give syntax error. Thanx, Phani On 9 Jun 2005 07:35:43 -0000, muthyala sirish kumar ... -- ... Pure love...
Hi Guys, Does anyone know about Static and Dynamic assertions in verification? I just know that Static assertions are based on mathamatical modelling and...
Thanks guys..I even tried that.. But the mistake was something else in some other part of the code!!! Silly fella I am.. :)) Thanks a lot for all ur...
Salam Nadeem, its pretty easy man, make use of "always" statement...I suggest you take basic verilog book and read "always" statment. Khuda hafiz Sridhar...
IEDCS'05 "2nd INTERNATIONAL ELECTRONICS DESIGN CONTEST FOR STUDENTS 2005" Handasa Arabia, University of Waterloo and IEEE ICM'05 are organizing the 2nd...
hello, i was wondering if anybody is familiar with this asynchronous micropipeline. or anybody has done some verilog programming for asynchronous design ...
Wanted ASIC, RTL coding with Verilog / VHDL programmers on contract in Korea. Hi, We have immediate requirements for ASIC, RTL coding with Verilog / VHDL...
hi , plz anyone that can help me designing the program in verilog for viterbi decoder and convolutional encoder.i got the algorithm but facing problems in...
hi all of u there, i m new member of this group. friends i m doing m tech & working on a verilog project. i m doing direct form FIR filter modeling in verilog....
Whatz the algorithm? Can give it a try. adeel ahmed <madeel_ahmed2003@...> wrote:hi , plz anyone that can help me designing the program in verilog for...
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