Wanted ASIC, RTL coding with Verilog / VHDL programmers on contract in Korea. Hi, We have immediate requirements for ASIC, RTL coding with Verilog / VHDL...
hi , plz anyone that can help me designing the program in verilog for viterbi decoder and convolutional encoder.i got the algorithm but facing problems in...
hi all of u there, i m new member of this group. friends i m doing m tech & working on a verilog project. i m doing direct form FIR filter modeling in verilog....
Whatz the algorithm? Can give it a try. adeel ahmed <madeel_ahmed2003@...> wrote:hi , plz anyone that can help me designing the program in verilog for...
thanks for replying me .Actually the i need a help in programming a shift register using D flip flops with serial in data and parallel out.if u guys can help...
Hi sorry for the late reply.......did you get the code or are you in need? I think I already have a code written for a Serialin, Parallel out shift reg for one...
thanks for replying me bhavana.sorry there is little mistake from my side is that i really in need of 2 bits parallel to serial converter.so if can provide it...
Hello, Everybody, hope every body is doing fine. I need a help please do give me some FAQ's or interview questions asked on verilog. and also if there are any...
hi, i need some help for my term project(VERILOG CODE FOR A 2 WAY SET ASSOCIATIVE CACHE CONTROLLER).if you know any of your friends who is good at verilog hdl...
We are seeking exceptional candidates for our client, a world leader in Memory Solutions. Headquartered in the US. Having recently started their development...
Dear Friends, I have written a verilog code for a module. I have synthesized it with Synplify Pro for a Virtex II Pro chip and it has given me an edif netlist...
Our client, a world leader in Visual Computing Technology is seeking Sr. BIOS Engineer for their operations in Bangalore. The incumbent is expected to guide,...
JOIN VERILOG_UET@YAHOOGROUPS.COM hi people i m doing lot of research on verilog from last 8-10 yrs or so. I want ur participation in group verilog_uet where...
JOIN VERILOG_UET@YAHOOGROUPS.COM hi people i m doing lot of research on verilog from last 8-10 yrs or so. I want ur participation in group verilog_uet where...
hi, friend lookup table is jst like a simple table against each value u have other value. Jst like u go to shop and demand for some item and he tells u price....
i m a new member.actually i wanna ask abt the generate command and therelated command like degenrate genvar etc.veriwell is not recognizing these commands. so...
Our client, a World leader in Visual Computing Technology is seeking System Engineer for their operations in Bangalore. The incumbent is expected to guide,...
Are you using VeriWell? I haven't maintained it in about 7 years, so it will not have 2001 features, like Generate. Anyone else still using VeriWell? I...
thanks alot Elliot for ur response.so what should i do.i should be working n veriwell or some other good software.actually i wanna do my final year project in...
... I hope that's not the same software Synapticad is selling for a minimum of $1,500 per copy!? See: http://xrl.us/g59s If so, I hope you're getting...
SynaptiCAD's simulator started with VeriWell, but I imagine it has been heavily modified by now. I am considering making VeriWell open source. It is a classic...
Can -you help- me in replacing -for loops -with if_else statements or counters code with for loop for(a=63;a>=16;a=a-1) begin //message4[a=63]inverted //takes...
hi fareha well first all i would like to tell u that always avoid using for loops coz it may cause probs during synthesis. 2ndly try this change if(a>=16) ...
Thanks alot I'll check and see if these changes work,is there any software which can automatically generate state machine and block diagrams from verilog...
hi fakeha well yes u can generate fsm using xilinx, aldec or altera's max plus II i dunno abt FPGA advantage.............its model sim i think. and yes when u...
Hi Mona firstly i was using xilinx ISE 6.2 ,i wrote my verilog code but when i tried to synthesize the code i received errors (low virtual memory)now i thought...
Hi all, I am facing lots of problem in ASIC and FPGA design Flow. Prob1, in ASIC design Flow where layout preparation comes into the picture . Prob2. How...
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