Hi, This is shruthi from Alphaeus HR;One of our client an American MNC and a world leader in Graphics Technology , now has recently opened their operations in...
Hi Shruti, This is Nishit. I am working as EDA engineer at present in ahmedabad based company. Here are the list of key skills of mine. C/C++ programming in...
Hi, This is shruthi from Alphaeus HR;One of our client an American MNC and a world leader in Graphics Technology , now has recently opened their operations in...
Hi, This is shruthi from Alphaeus HR;One of our client an American MNC and a world leader in Graphics Technology , now has recently opened their operations in...
You can use a LFSR (Linear Feedback Shift Register) to build a pseudo random bit generator. Which should be able to meet your needs. Good Luck, Grifter13 ... ...
Place and Route Sr. EDA Developer Responsibilities: The candidate will be responsible for designing & developing tools related to P&R system. Domain knowledge...
Hi, We have immediate requirements for VC++, MFC system level programmers for our MNC client in Chennai. Primary Skills : VC++, MFC, COM Experience in system...
Hi friends, Can any one suggest me how to write the VHDL code of IO blocks or any material regarding that? Regards Gurleen.. ... What are the most...
hi friend! refer VERILOG DESIGN by PALNITKAR VIPUL MISTRY Gurleen <aroragurleen@...> wrote: Hi friends, Can any one suggest me how to write the VHDL code...
hello... Which type of IO blocks...do you want to write just behavioral models...u can fallow the vendor library bocks and they will give buffer input and...
Hi, We have immediate requirements for DSP Engineers for our MNC client in Bangalore, India. Skillset : Experience in DSP environment (TI, ADI) Experience in...
Hi, We have immediate requirements for Embedded Engineers for our MNC client in Bangalore, India. Skillset : Development experience on device drivers, ...
Hi, We have immediate requirements for Tech Lead -Win CE for our MNC client in Bangalore, India. Skillset : C,C++, EVC++ ,Device Driver , SDK, Win 32 prog ,...
Hi!! I am trying to make a module in which there are two loops one inside the other. I am tring to pipeline the inner loop. I had made the module using FSM. My...
hii.... i am implementing an folded arch. for fir filter for improving its hardware efficiency.my proj is based on article "pipelined array based fir filter...
Hi everybody.. I have questions. Does timescale affect rtl (not gate level) simulation speed especially for big design? For example, 1) 1 ns/1 ns 2) 1 ns / 100...
i guess it will get affected..... best to way to know that...just try these changes into ur code .....& see what happens next ..also dont forget to post the...
Hi, We have an excellent opportunity with World-leading EDA software and IP Design Company. They provide solutions and products in advanced memory systems for...
Hi, We have immediate requirements for Board Design Engineers for our MNC client in Bangalore. Location : Bangalore. Experience : 6+ years. Job type :...
Hello All, Can you help me in creating a checkerboard for thi test bench module tb (); reg clk; reg bist_start; reg reset; wire [6:0] address; wire [71:0]...
Hi, We have immediate requirements for Senior Board / System Design Engineer for our client in Bangalore. Skillset : Experience in # Board Design with Motorola...
Hello kalaivani, Can you describe a bit in more detail on you problem. What exactly are you trying to do?? verilog@yahoogroups.com wrote: There is 1 message in...
that is compilation is fine but when simulation starts it says tht cp(copy command) is not known to that tool but i hv verified it tht thr is cp.exe for tht...
testcases passes when it is run individually , but when ran in batch it fails, y(eventhough i adjusted the simulation time) kalaivani ... Blab-away for as...
hi There may be several problems. check if the sim.log created has not appropriate permission to be overwrriten by u . check in the script is the file sim.log...
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