Hi, We have immediate requirements for DSP Engineers for our MNC client in Bangalore, India. Skillset : Experience in DSP environment (TI, ADI) Experience in...
Hi, We have immediate requirements for Embedded Engineers for our MNC client in Bangalore, India. Skillset : Development experience on device drivers, ...
Hi, We have immediate requirements for Tech Lead -Win CE for our MNC client in Bangalore, India. Skillset : C,C++, EVC++ ,Device Driver , SDK, Win 32 prog ,...
Hi!! I am trying to make a module in which there are two loops one inside the other. I am tring to pipeline the inner loop. I had made the module using FSM. My...
hii.... i am implementing an folded arch. for fir filter for improving its hardware efficiency.my proj is based on article "pipelined array based fir filter...
Hi everybody.. I have questions. Does timescale affect rtl (not gate level) simulation speed especially for big design? For example, 1) 1 ns/1 ns 2) 1 ns / 100...
i guess it will get affected..... best to way to know that...just try these changes into ur code .....& see what happens next ..also dont forget to post the...
Hi, We have an excellent opportunity with World-leading EDA software and IP Design Company. They provide solutions and products in advanced memory systems for...
Hi, We have immediate requirements for Board Design Engineers for our MNC client in Bangalore. Location : Bangalore. Experience : 6+ years. Job type :...
Hello All, Can you help me in creating a checkerboard for thi test bench module tb (); reg clk; reg bist_start; reg reset; wire [6:0] address; wire [71:0]...
Hi, We have immediate requirements for Senior Board / System Design Engineer for our client in Bangalore. Skillset : Experience in # Board Design with Motorola...
Hello kalaivani, Can you describe a bit in more detail on you problem. What exactly are you trying to do?? verilog@yahoogroups.com wrote: There is 1 message in...
that is compilation is fine but when simulation starts it says tht cp(copy command) is not known to that tool but i hv verified it tht thr is cp.exe for tht...
testcases passes when it is run individually , but when ran in batch it fails, y(eventhough i adjusted the simulation time) kalaivani ... Blab-away for as...
hi There may be several problems. check if the sim.log created has not appropriate permission to be overwrriten by u . check in the script is the file sim.log...
Hi, I just started learning verilog. I am facing difficulty in compiling and executing verilog programs using Icarus Verilog in Windows. Can anyone list the...
Perhaps you will find it easier to use VeriWell: http://sourceforge.net/projects/veriwell _____ From: verilog@yahoogroups.com [mailto:verilog@yahoogroups.com]...
Hi, Just follow the steps for compiling and execute 1. D:\iverilog>iverilog Fulladder.v for compiling the verilog code ...u can give more than one no of...
Icarus Verilog is a free verilog simulator. You can find more about this here http://www.icarus.com/eda/verilog/ Goverdhan. kalai vani <premrajan_18@...>...
Hello Everyone, I have started a group cadence_university for the institutes comming under cadence university.Faculty members of institutes comming under ...
1.hw do u say a processor as an 8 bit / 16 bit one , by means of addr lines r data lines 2.wht do u mean by APEX20KE devices and wht do u mean by speed-grade...
hello kalai vani, here are some of the answers to ur ques?? * - don't have much idea ****** - reply soon with details 1.hw do u say a processor as an 8 bit /...
Parag, I hope you were joking about CTS being Congnizant...!! In this context, CTS refers to Clock Tree Synthesis. Regards Ganesh ASIC Verification Engineer, ...
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