Hi everybody.. I have questions. Does timescale affect rtl (not gate level) simulation speed especially for big design? For example, 1) 1 ns/1 ns 2) 1 ns / 100...
i guess it will get affected..... best to way to know that...just try these changes into ur code .....& see what happens next ..also dont forget to post the...
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Hello All, Can you help me in creating a checkerboard for thi test bench module tb (); reg clk; reg bist_start; reg reset; wire [6:0] address; wire [71:0]...
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Hello kalaivani, Can you describe a bit in more detail on you problem. What exactly are you trying to do?? verilog@yahoogroups.com wrote: There is 1 message in...
that is compilation is fine but when simulation starts it says tht cp(copy command) is not known to that tool but i hv verified it tht thr is cp.exe for tht...
testcases passes when it is run individually , but when ran in batch it fails, y(eventhough i adjusted the simulation time) kalaivani ... Blab-away for as...
hi There may be several problems. check if the sim.log created has not appropriate permission to be overwrriten by u . check in the script is the file sim.log...
Hi, I just started learning verilog. I am facing difficulty in compiling and executing verilog programs using Icarus Verilog in Windows. Can anyone list the...
Perhaps you will find it easier to use VeriWell: http://sourceforge.net/projects/veriwell _____ From: verilog@yahoogroups.com [mailto:verilog@yahoogroups.com]...
Hi, Just follow the steps for compiling and execute 1. D:\iverilog>iverilog Fulladder.v for compiling the verilog code ...u can give more than one no of...
Icarus Verilog is a free verilog simulator. You can find more about this here http://www.icarus.com/eda/verilog/ Goverdhan. kalai vani <premrajan_18@...>...
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1.hw do u say a processor as an 8 bit / 16 bit one , by means of addr lines r data lines 2.wht do u mean by APEX20KE devices and wht do u mean by speed-grade...
hello kalai vani, here are some of the answers to ur ques?? * - don't have much idea ****** - reply soon with details 1.hw do u say a processor as an 8 bit /...
Parag, I hope you were joking about CTS being Congnizant...!! In this context, CTS refers to Clock Tree Synthesis. Regards Ganesh ASIC Verification Engineer, ...
I don't know how to execute code in silos can anyone help me in this way about whole procedure of the silos to run the code? ... Jiyo cricket on Yahoo! India...
hello ganesh, u say that i am joking, but i just answered it b'coz some of the questions send were very much incomplete. therefore, i request everyone that...
Hi always @(*) begin <statements> end What the * indicates and what the code does?... ... Blab-away for as little as 1¢/min. Make PC-to-Phone Calls using...
Hi, If you put * in the seneitivity list of a always block, all of the necessary signals which have to be in the sensitivity list, will be considered as ...
Thank you mohsen... Mohsen Yousefpour <m.yousefpour@...> wrote: Hi, If you put * in the seneitivity list of a always block, all of the necessary signals...
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