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Messages 575 - 604 of 735   Oldest  |  < Older  |  Newer >  |  Newest
Messages: Simplify | Expand   (Group by Topic) Author Sort by Date ^
575
no freshers plz POSITIONS Wireless Group: Verification Engg / Team Lead / Project Manager (Exp level – 2 to 10 yrs) Job Description: RTL, Testbench... 		vikasamit2000
Offline Send Email 		Apr 3, 2006
5:49 am
576
while using perl script to run in batch, sim.log is not updated. hw to correct this .plz answer... 		kalaivani
premrajan_18
Offline Send Email 		Apr 10, 2006
10:57 am
577
Hello kalaivani, Can you describe a bit in more detail on you problem. What exactly are you trying to do?? verilog@yahoogroups.com wrote: There is 1 message in... 		parag goel
paraggoel2003
Offline Send Email 		Apr 11, 2006
10:13 am
578
that is compilation is fine but when simulation starts it says tht cp(copy command) is not known to that tool but i hv verified it tht thr is cp.exe for tht... 		kalai vani
premrajan_18
Offline Send Email 		Apr 11, 2006
11:51 am
579
testcases passes when it is run individually , but when ran in batch it fails, y(eventhough i adjusted the simulation time) kalaivani ... Blab-away for as... 		kalai vani
premrajan_18
Offline Send Email 		Apr 11, 2006
11:56 am
580
hi There may be several problems. check if the sim.log created has not appropriate permission to be overwrriten by u . check in the script is the file sim.log... 		rajendra kumar
rajendra_itbhu
Offline Send Email 		Apr 11, 2006
12:54 pm
581
Hi, I just started learning verilog. I am facing difficulty in compiling and executing verilog programs using Icarus Verilog in Windows. Can anyone list the... 		madipadiga goverdhan
justgova212
Online Now Send Email 		Apr 11, 2006
4:31 pm
582
Perhaps you will find it easier to use VeriWell: http://sourceforge.net/projects/veriwell _____ From: verilog@yahoogroups.com [mailto:verilog@yahoogroups.com]... 		Elliot Mednick
elliot00
Offline Send Email 		Apr 11, 2006
5:41 pm
583
wat do u mean by icarus verilog Elliot Mednick <elliot@...> wrote: Perhaps you will find it easier to use VeriWell:... 		kalai vani
premrajan_18
Offline Send Email 		Apr 12, 2006
2:42 am
584
Hi, Just follow the steps for compiling and execute 1. D:\iverilog>iverilog Fulladder.v for compiling the verilog code ...u can give more than one no of... 		pari krishnan
spari_11
Offline Send Email 		Apr 12, 2006
4:49 am
585
Hi, Thanks for the link. Goverdhan. Elliot Mednick <elliot@...> wrote: Perhaps you will find it easier to use VeriWell:... 		madipadiga goverdhan
justgova212
Online Now Send Email 		Apr 12, 2006
7:07 am
586
Icarus Verilog is a free verilog simulator. You can find more about this here http://www.icarus.com/eda/verilog/ Goverdhan. kalai vani <premrajan_18@...>... 		madipadiga goverdhan
justgova212
Online Now Send Email 		Apr 12, 2006
7:08 am
587
Hi... Thanks for the help. It works. Goverdhan. pari krishnan <spari_11@...> wrote: Hi, Just follow the steps for compiling and execute 1.... 		madipadiga goverdhan
justgova212
Online Now Send Email 		Apr 12, 2006
7:09 am
588
Hello Everyone, I have started a group cadence_university for the institutes comming under cadence university.Faculty members of institutes comming under ... 		Siddharth
deosiddharth
Offline Send Email 		Apr 12, 2006
10:26 am
589
1.hw do u say a processor as an 8 bit / 16 bit one , by means of addr lines r data lines 2.wht do u mean by APEX20KE devices and wht do u mean by speed-grade... 		kalai vani
premrajan_18
Offline Send Email 		Apr 13, 2006
5:47 am
590
hello kalai vani, here are some of the answers to ur ques?? * - don't have much idea ****** - reply soon with details 1.hw do u say a processor as an 8 bit /... 		parag goel
paraggoel2003
Offline Send Email 		Apr 17, 2006
10:33 am
591
Parag, I hope you were joking about CTS being Congnizant...!! In this context, CTS refers to Clock Tree Synthesis. Regards Ganesh ASIC Verification Engineer, ... 		Ganesh T S
vlsi_comparch
Offline Send Email 		Apr 17, 2006
4:27 pm
592
I don't know how to execute code in silos can anyone help me in this way about whole procedure of the silos to run the code? ... Jiyo cricket on Yahoo! India... 		milan pujara
milan_9706
Offline Send Email 		Apr 18, 2006
3:17 pm
593
hello ganesh, u say that i am joking, but i just answered it b'coz some of the questions send were very much incomplete. therefore, i request everyone that... 		parag goel
paraggoel2003
Offline Send Email 		Apr 20, 2006
9:43 am
594
Hi always @(*) begin <statements> end What the * indicates and what the code does?... ... Blab-away for as little as 1¢/min. Make PC-to-Phone Calls using... 		Satish
msatish_asic
Offline Send Email 		Apr 21, 2006
12:46 am
595
Hi, If you put * in the seneitivity list of a always block, all of the necessary signals which have to be in the sensitivity list, will be considered as ... 		Mohsen Yousefpour
yousef_p_m
Offline Send Email 		Apr 21, 2006
5:46 am
596
Thank you mohsen... Mohsen Yousefpour <m.yousefpour@...> wrote: Hi, If you put * in the seneitivity list of a always block, all of the necessary signals... 		Satish
msatish_asic
Offline Send Email 		Apr 21, 2006
4:11 pm
597
hello satish, here are some of the explainations qouted from various papers:: i hope these details answers ur question? ******************************** 3.10... 		parag goel
paraggoel2003
Offline Send Email 		Apr 22, 2006
6:21 am
598
Hi, Does anybody know of a free timing diagram tool to draw timing diagrams and also save the files(I am aware of timinggen, www.timingtool.com, etc). Regards,... 		indu_14
Offline Send Email 		Apr 25, 2006
5:56 pm
599
Hi, We have requirement for Firmware Developers with 3+yrs of experience for our client in Hyderabad. So if you are interested, kindly do forward your updated... 		Prabhu Santhanam
prabhusanthanam
Offline Send Email 		Apr 26, 2006
3:18 pm
600
Hi, We have requirement for Firmware Developers with 3+yrs of experience for our client in Hyderabad. So if you are interested, kindly do forward your updated... 		Prabhu Santhanam
prabhusanthanam
Offline Send Email 		Apr 27, 2006
11:37 am
601
Hi All, Do anyone have an Idea on Posted, Non-posted, Completion transactions...if so can you give me a little explanation. Thanks Satish ... How low will we... 		Satish
msatish_asic
Offline Send Email 		Apr 28, 2006
4:30 pm
602
Hi all. I've done a fair bit of Abel HDL coding, but am trying to learn Verilog now. It's certainly different! First simple question: I haven't come across... 		Michael Dunn
ambisonx
Offline Send Email 		May 2, 2006
1:13 am
603
hii... can any ofu suggest solution for clearing an warnig in xilinx xst:1290 while synthesising a codein verilog... thanks, arun. ... Talk is cheap. Use... 		arun prasath
chipbrain2003
Offline Send Email 		May 2, 2006
4:20 am
604
Hi Michael If i got you write F11M = "(sel == 'b001)"; F12M = "(sel == 'b000)"; F16M = "(sel == 'b110)"; if (F11M || F12M || F16M) then ... also if((sel ==... 		Vikramaditya Kundur
vikadik
Offline Send Email 		May 2, 2006
2:35 pm
Messages 575 - 604 of 735   Oldest  |  < Older  |  Newer >  |  Newest
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