verilog : Messages : 60-89 of 735

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60	what does this statement do in hardware ? assign out = {A[31] , A[31:1]};...	aaditya_goswami	Mar 2, 2002 2:39 pm
61	If out is a 32 bit bus, it will do a left shift with carry extension out[31] = A[31] out[30:0] = A[31:1] A[0} will be lost MHMinai ... ...	Mohammad Haris Minai mohd_haris	Mar 3, 2002 6:04 pm
62	Hi Aaditya, That stmt would do the sign-extension keeping the number of bits constant. rama ... __________________________________________________ Do You...	Rama Lolla maninhills	Mar 3, 2002 7:54 pm
63	Implementation wise, it is concatentation of the respective bits. out = {A[31], A[31], A[30], A[29], ................ A[1]} A[0] is lost Effectively it is a...	faysaladeem	Mar 4, 2002 12:57 pm
64	// Generated by ac_shell v4.0-s002 on Mon Mar 04 07:31:57 PST 2002. // Restrictions concerning the use of Ambit BuildGates are covered in the // license...	david_hollinbeck@...	Mar 4, 2002 3:35 pm
65	hi, well how can such lines be implemented in veilog a=0.25x-0.375y+4z+w; reply soon fatima __________________________________________________ Do You Yahoo!? ...	Fatima Nayyar nayyarfatima	Mar 5, 2002 4:01 pm
66	Making the code synthesizable it is a non-trivial issue, if you want to use this in a testbench, "real" variables in verilog can help, as an example real a, x,...	Mohammad Haris Minai mohd_haris	Mar 6, 2002 11:11 am
67	I guess people here might be interested in joining the "hdlplanet" group @ http://groups.yahoo.com/group/hdlplanet Also.... may be interested in visiting the...	harishys	Mar 12, 2002 5:49 am
68	Hi, I have downloaded these free tools. I have a problem. Whenever I try to build a file around 100 lines, the whole window disappears (win 98). This happens...	techvhk	Mar 12, 2002 10:01 pm
69	Hi, I am looking for an interleaver design program in Verilog. Any pointers? HK...	techvhk	Mar 12, 2002 10:03 pm
70	hi, i m working on synapticad. u have evaluatoin copy or something else , i mean full version if u have that code which closes the window send me i will telkl...	Fatima Nayyar nayyarfatima	Mar 13, 2002 2:28 am
71	Hi, I am trying to install modelsim evaluation version. It is asking for some licence. How to get it? HK __________________________________________________ Do...	HK techvhk	Mar 13, 2002 4:56 am
72	Got to: www.astalavista.box.sk and type in 'modelsim'. Otherwise go to mentor site and search for eval-version request form. Regards mpr....	Marc Rawer marc_rawer	Mar 13, 2002 12:20 pm
73	Hi, In general I would like to know what are the free tools for verilog. I need to do some student assignments. rgds HK ... ...	HK techvhk	Mar 13, 2002 5:57 pm
74	hi guys, I want to design a 7 to 128 line decoder using verilog. Its pretty stupid to like...mention 128 outputs for all possible combinations of inputs. ...	Aditya Goswami aaditya_goswami	Mar 28, 2002 8:36 pm
75	Hi, You could do: input [6:0] decode_in ; output [127:0] decode_out ; begin decode_out = 128'b0; decode_out[decode_in] = 1'b1; end Or you could use a for loop...	jstahl@... bellweather4	Mar 28, 2002 8:49 pm
76	hi guys, thankyou for your reply. I had another question. If I want to build a ckt. where in : if line no : 12 is high...then....lines 0 thru 11 are high..the...	Aditya Goswami aaditya_goswami	Mar 28, 2002 11:39 pm
77	Hi all, I am a graduate student at University of Florida. I am new to the concept of hardware design using verilog. I am implementing a Chirp-Z 4-point...	maninhills	Mar 31, 2002 11:10 pm
78	hi, does any one know how to implement a 6 bit carry lookahead adder or a 6 input carry save adder with a 4 bit output using verilog ?? regards, aditya ...	Aditya Goswami aaditya_goswami	Apr 3, 2002 8:15 pm
79	Aditya its not difficult if u have understood it well. C the method and implement it in the same manner in verilog. For 4 bit output set the size of the output...	Fatima Nayyar nayyarfatima	Apr 4, 2002 4:34 am
80	AOA , I need information abt PCI driver , although i have searched on net but didnt find anything. I m making GUI in VC ++ and using sockets then have to...	Fatima Nayyar nayyarfatima	Apr 4, 2002 2:31 pm
81	hi, how to generate random nubers in verylog? please send any one mail how to do this? kishore __________________________________________________ Do You...	tati kishore kishoretati	Apr 5, 2002 2:09 am
82	Use $random to assign a random number to a variable. Dave Hollinbeck tati kishore <kishoretati@yaho To: verilog@yahoogroups.com o.com>...	david_hollinbeck@...	Apr 5, 2002 4:56 pm
83	hello, i want to design a 8 bit adder in verilog,that must contain all the dalays like pin to pin clb and pad delays,what ever we get delay in xilinx for each...	tati kishore kishoretati	Apr 6, 2002 12:09 pm
84	Excellent I2C core for Altera, Xilinx and PLDs for $50.00. Im a FPGA designer and wacked off about two weeks from developing my own I2C interface. The great...	eileen_carlson2002 eileen_carls...	Apr 10, 2002 9:51 pm
85	hello, i want to design a 8 bit adder in verilog,that must contain all the dalays like pin to pin clb and pad delays,what ever we get delay in xilinx for each...	tati kishore kishoretati	Apr 12, 2002 4:32 am
86	hi, I am preparing a dram controller and a testfixture to control a standard Micron SDRAM. For the same , i require the controller to initialize states for the...	Aditya Goswami aaditya_goswami	Apr 15, 2002 10:46 pm
87	hi, Since you know that the nature of work of my organization is mostly R&D with emphasis on upgrading of exixting systems. We have existing systems already ...	Faysal Adeem faysaladeem	Apr 16, 2002 5:31 pm
88	You cannot specify a delay to a synthesis tool. What is best is to use a clock and a shift register or counter to get the delay you require. Dave Hollinbeck ...	david_hollinbeck@...	Apr 16, 2002 7:46 pm
89	Hello I am a beginner in Verilog scripting and i have to do very quick a project based on a display 6 rows by 4 coloumns , and the last row should be free.I...	patilinet	May 9, 2002 8:31 pm

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