hi, does any one know how to implement a 6 bit carry lookahead adder or a 6 input carry save adder with a 4 bit output using verilog ?? regards, aditya ...
Aditya its not difficult if u have understood it well. C the method and implement it in the same manner in verilog. For 4 bit output set the size of the output...
AOA , I need information abt PCI driver , although i have searched on net but didnt find anything. I m making GUI in VC ++ and using sockets then have to...
hi, how to generate random nubers in verylog? please send any one mail how to do this? kishore __________________________________________________ Do You...
Use $random to assign a random number to a variable. Dave Hollinbeck tati kishore <kishoretati@yaho To: verilog@yahoogroups.com o.com>...
david_hollinbeck@...
Apr 5, 2002 4:56 pm
83
hello, i want to design a 8 bit adder in verilog,that must contain all the dalays like pin to pin clb and pad delays,what ever we get delay in xilinx for each...
Excellent I2C core for Altera, Xilinx and PLDs for $50.00. Im a FPGA designer and wacked off about two weeks from developing my own I2C interface. The great...
hello, i want to design a 8 bit adder in verilog,that must contain all the dalays like pin to pin clb and pad delays,what ever we get delay in xilinx for each...
hi, I am preparing a dram controller and a testfixture to control a standard Micron SDRAM. For the same , i require the controller to initialize states for the...
hi, Since you know that the nature of work of my organization is mostly R&D with emphasis on upgrading of exixting systems. We have existing systems already ...
You cannot specify a delay to a synthesis tool. What is best is to use a clock and a shift register or counter to get the delay you require. Dave Hollinbeck ...
david_hollinbeck@...
Apr 16, 2002 7:46 pm
89
Hello I am a beginner in Verilog scripting and i have to do very quick a project based on a display 6 rows by 4 coloumns , and the last row should be free.I...
I am trying to implement the vco in verilog. can you help me in this implementation. Our requirement needs a sawtooth output. If you guide me I'll be...
Hello, This email message is a notification to let you know that a file has been uploaded to the Files area of the verilog group. File : / Looking for...
verilog@yahoogroups.com
May 28, 2002 7:45 pm
92
Hi All Verilog Yahoo-Group readers, Due to the amount of spam I've decided to make the membership moderated. To avoid problems when I'm away from my e-mail I ...
hello everybody please tell the name of the parser that synopsys uses for verilog and vhdl both in DC and formality and there support of latest verilog and...
hi is anybody implemented CORDIC(coordinate rotation digital computer) in verilog hdl plese helpme, i dont know about VHDL how can i conver VHDL code to...
... you can convert vhdl to verilog viseversa with "xhdl" software. by. ... __________________________________________________ Do You Yahoo!? Yahoo! - Official...
hi thanks for ur reply, please tell me is there is any freewere of xhdl(to conver vhdl to verilog hdl) bye pradeep ... <HR> <html><body> <tt> <BR> ... ...
Here is the cordic core written in verilog. http://www.free-ip.com/cordic/index.html regards, -Rohit ... From: "gpradeep14" <gpradeep14@...> Reply-To:...
Hi Moderator, If you wish i can help you out in this by becoming moderator (well if the option is still open). As i am already moderator for my college and...
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Dear Mr. Jo, I'd like to send you my resume as an attachment. I am looking for a job in Analog and Mixed IC design engineers and Firmware Engineers. Kindly let...
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