I am using Windows XP SP2. Attached the faulty file.

JDem

Khan Kibria a écrit :
> Send me the zipped or gziped VCD file. What windows are you running?
>
> ----- Original Message -----
> From: "Jean DEMARTINI" <jean.demartini@...>
> To: <wavevcd@yahoogroups.com>
> Sent: Thursday, April 13, 2006 1:25 AM
> Subject: [wavevcd] Wave VCD "core dump"
>
>
> > Wave VCD encounters a nasty problem when dealing with 32 bits
> > registers. My design VCD chrono. is correctly displayed when the data
> > size (reg size) is 16 bits but crashes (with the apologies of Windows)
> > when data size is 32 bits.
> >
> > JDem
>
>
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----------

$date
Thu Apr 13 18:10:52 2006
$end
$version
Icarus Verilog
$end
$timescale
1ns
$end
$scope module main $end
$var wire 1 ! clk $end
$var wire 1 " tst $end
$var reg 16 # N[15:0] $end
$var reg 16 $ U[15:0] $end
$scope module tick $end
$var wire 1 " stp $end
$var reg 1 ! clk $end
$upscope $end
$scope module comp $end
$var wire 1 % ALE $end
$var wire 1 & ASEL $end
$var wire 1 ' BLE $end
$var wire 1 ( BSEL $end
$var wire 16 ) N[15:0] $end
$var wire 2 * Q[1:0] $end
$var wire 16 + U[15:0] $end
$var wire 16 , ai[15:0] $end
$var wire 16 - ao[15:0] $end
$var wire 16 . av[15:0] $end
$var wire 16 / bi[15:0] $end
$var wire 16 0 bo[15:0] $end
$var wire 16 1 bv[15:0] $end
$var wire 1 ! clk $end
$var wire 1 " tst $end
$scope module Amux $end
$var wire 16 2 inp0[15:0] $end
$var wire 16 3 inp1[15:0] $end
$var wire 16 4 out[15:0] $end
$var wire 1 & sel $end
$upscope $end
$scope module Bmux $end
$var wire 16 5 inp0[15:0] $end
$var wire 16 6 inp1[15:0] $end
$var wire 16 7 out[15:0] $end
$var wire 1 ( sel $end
$upscope $end
$scope module Areg $end
$var wire 1 % LE $end
$var wire 16 8 inp[15:0] $end
$var reg 16 9 out[15:0] $end
$upscope $end
$scope module Breg $end
$var wire 1 ' LE $end
$var wire 16 : inp[15:0] $end
$var reg 16 ; out[15:0] $end
$upscope $end
$scope module mul $end
$var wire 16 < inp1[15:0] $end
$var wire 16 = inp2[15:0] $end
$var wire 16 > out[15:0] $end
$upscope $end
$scope module dec $end
$var wire 16 ? inp[15:0] $end
$var wire 16 @ out[15:0] $end
$upscope $end
$scope module test $end
$var wire 16 A inp[15:0] $end
$var wire 1 " tst $end
$upscope $end
$scope module fsm $end
$var wire 1 ! clk $end
$var wire 1 " inp $end
$var reg 2 B Q[1:0] $end
$var reg 4 C out[3:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 C
b0 B
bx A
bx @
bx ?
bx >
bx =
bx <
bx ;
b111 :
bx 9
b1 8
b111 7
bx 6
b111 5
b1 4
bx 3
b1 2
bx 1
b111 0
bx /
bx .
b1 -
bx ,
b1 +
b0 *
b111 )
0(
0'
0&
0%
b1 $
b111 #
x"
0!
$end
#1
b1 *
b1 B
1!
#2
0!
#3
0"
b111 -
b111 4
b111 8
b110 0
b110 7
b110 :
b111 ,
b111 3
b111 >
b1 .
b1 9
b1 <
b110 /
b110 6
b110 @
b111 1
b111 ;
b111 =
b111 ?
b111 A
b10 *
b10 B
1&
1(
1%
1'
b1111 C
1!
#4
0%
0'
b1100 C
0!
#5
b101010 -
b101010 4
b101010 8
b101 0
b101 7
b101 :
b111 .
b111 9
b111 <
b101010 ,
b101010 3
b101010 >
b101 /
b101 6
b101 @
b110 1
b110 ;
b110 =
b110 ?
b110 A
1%
1'
b1111 C
1!
#6
0%
0'
b1100 C
0!
#7
b11010010 -
b11010010 4
b11010010 8
b100 0
b100 7
b100 :
b101010 .
b101010 9
b101010 <
b11010010 ,
b11010010 3
b11010010 >
b100 /
b100 6
b100 @
b101 1
b101 ;
b101 =
b101 ?
b101 A
1%
1'
b1111 C
1!
#8
0%
0'
b1100 C
0!
#9
b1101001000 -
b1101001000 4
b1101001000 8
b11 0
b11 7
b11 :
b11010010 .
b11010010 9
b11010010 <
b1101001000 ,
b1101001000 3
b1101001000 >
b11 /
b11 6
b11 @
b100 1
b100 ;
b100 =
b100 ?
b100 A
1%
1'
b1111 C
1!
#10
0%
0'
b1100 C
0!
#11
b100111011000 -
b100111011000 4
b100111011000 8
b10 0
b10 7
b10 :
b1101001000 .
b1101001000 9
b1101001000 <
b100111011000 ,
b100111011000 3
b100111011000 >
b10 /
b10 6
b10 @
b11 1
b11 ;
b11 =
b11 ?
b11 A
1%
1'
b1111 C
1!
#12
0%
0'
b1100 C
0!
#13
b1001110110000 -
b1001110110000 4
b1001110110000 8
b1 0
b1 7
b1 :
b100111011000 .
b100111011000 9
b100111011000 <
b1001110110000 ,
b1001110110000 3
b1001110110000 >
b1 /
b1 6
b1 @
b10 1
b10 ;
b10 =
b10 ?
b10 A
1%
1'
b1111 C
1!
#14
0%
0'
b1100 C
0!
#15
b1001110110000 -
b1001110110000 4
b1001110110000 8
b0 0
b0 7
b0 :
b1001110110000 .
b1001110110000 9
b1001110110000 <
b1001110110000 ,
b1001110110000 3
b1001110110000 >
b0 /
b0 6
b0 @
b1 1
b1 ;
b1 =
b1 ?
b1 A
1%
1'
b1111 C
1!
#16
0%
0'
b1100 C
0!
#17
1"
b0 -
b0 4
b0 8
b1111111111111111 0
b1111111111111111 7
b1111111111111111 :
b0 ,
b0 3
b0 >
b1111111111111111 /
b1111111111111111 6
b1111111111111111 @
b0 1
b0 ;
b0 =
b0 ?
b0 A
1%
1'
b1111 C
1!


[Non-text portions of this message have been removed]