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I was just wondering if your core had a timing compatibility mode, or if it only runs flat out? Assuming it only runs at the high speed, do you think it would be hard to adapt?
cya, Andrew...
-----Original Message-----All:
From: Brewster J Porcella [mailto:bporcella@...]
Sent: Sunday, 18 April 2004 1:10 AM
To: zxgate@yahoogroups.com
Subject: [zxgate] Z80 Instruction Test
I am building a Z80 Core on OpenCores. This core differs from the
t80 core that some of you are familiar with in a couple of ways..
1) Written in verilog
2) designed for SoC applications (not as a standalone FPGA)
3) Designed to optomize use of internal ASIC SRAM - its fast.
The processor is more complicated than I had origionally anticipated -
so project is proceeding slower than I had expected. However, I
should be into verification in a matter of weeks.
I have seen reference to an instruction "exercizer" on these pages.
Can anyone out there point me to a good test (hopefully written in
assembly language) that verifies proper instruction execution ?
bj
(btw - if anyone wishes to help with the verification process - let
me know - need all the help I can get)
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